Q20000 Search Results

Contextual Info: >4MCC Q20000 "T U R B O ECL/TTL TIMING VERNIERS TIMING VERNIER PD01S Figure 16. Functional Block Diagram The PD01S is a programmable delay macro in the Q20000 TU R B O ” family that provides a timing genera­ tion or deskew function for precision timing applications

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

carry look ahead adder

Abstract: Q20010 Q20120 Q20000
Contextual Info: DEVICE SPECIFICATION LOGIC A R R A Y S 020000 Q20000 FEATURES T U R B O ” ECL/TTL Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 100KECL and mixed ECL/TTL capability

signal path designer

Contextual Info: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability

diode BY 399 itt

Abstract: Q20P010 M/Q20P025
Contextual Info: DEVICE SPECIFICATION ECL/TTL “TURBO ” LOGIC ARRAYS WITH PHASE-LOCKED LOOP Q20P010/Q20P025 FEATURES On-chip high frequency phase-locked loop Up to 1.25 GHz capability Edge jitter as low as 50 ps pk-pk 900 and 3000 gates of customizable digital logic Utilizes proven Q20000* Series macro library

TTL 1980

Contextual Info: jQM CXZ O P ER ATIN G CONDITION'S Q20000 "T U R B O ’ E C L/TTL Table 19. Recommended Operating Condhlons-Commerclal Parameter ECL Supply Voltage1* V « V CC« 0 10K, 10KH Mode 100K Mode Min Norn Max Units -4.94 -4.2 -5.2 -4.5 -5.46 -4.83 V V 1.0 3.0

iacqc

Abstract: G2Q000 lnklp
Contextual Info: JX fA Q20000 T U R B O ‘ PLL C C LOGIC A R R A Y S WITH ON-CHIP P L Ls FEATURES Figure 10. Q20000 “TURBO” + PLL Architecture • On-chip high frequency phase-locked loop I— - Phase Detector • Up to 1.25 GHz capability • Edge jitter as low as 10ps rms) and 50 ps (pk-pk)

Contextual Info: E C L in P S TO ASIC C O NVERSIO N JX,M C C AM C C AS IC S DESCRIPTION AMCC offers turnkey solutions in a small ASIC that is tailored for the integration of discrete ECLinPS logic. Using the Q20004 gate array and the exten­ sive Q20000 "TURBO" ECL/TTL macro library,

CHN 920 diode

Abstract: q20120 CHN 816
Contextual Info: APPLIED MICRO CIRCUITS OÔÔTGDS 0000032 434 « A M C C T -H Z - I I ' ¡S' S1E D DEVICE SPECIFICATION Q20000 SER IES ECL/TTL “T U R B O ” LOGIC ARRAYS Q20000 FEATURES Up to 18,700 gates, channelless architecture 100 ps equivalent gate delays Ultra low power .5-1.0 mW/gate

Contextual Info: Automotive Grade Ceramic Chip Capacitors NMA Series FEATURES • MANUFACTURED AT ISO/TS 16949 PRODUCTION FACILITY • AEC-Q200 QUALIFIED • SURFACE MOUNT CASE SIZES 0402, 0603, 0805 & 1206 • AVAILABLE IN NPO & X7R DIELECTRICS • AVAILABLE WITH FLEX TERMINATIONS & OPEN MODE

LRMA

Abstract: lrmat2512
Contextual Info: LRMA Low Resistance Metal Alloy Current Sense Resistor • • • • • Robust metal strip able to withstand high temperature and high current. Low TCR and Inductance Resistance Range from 1 mΩ to 100 mΩ Power ratings from 1W to 3W in 0815, 1206, and 2512 chip size

ceramic capacitor 103 aec

Abstract: EIA-469 ceramic capacitor 102 aec Fr4 ep-gc-02 "Piezoelectric Sensor" Vishay quality iso certificate VJ Safety Certified Capacitors C0G (NP0) VJ0402 VJ0603 VJ1206
Contextual Info: VJ.31/VJ.34 Automotive MLCC Vishay Vitramon Surface Mount Multilayer Ceramic Chip Capacitors for Automotive Applications FEATURES • Surface mount, precious metal technology, wet build process • Available in 0402 to 1812 body size • Four dielectric materials

LRMA

Contextual Info: Low Resistance Metal Alloy Current Sense Resistor LRMA Series • • • • • Robust metal strip able to withstand high temperature and high current. Low TCR and Inductance Resistance Range from 1 mΩ to 100 mΩ Power ratings from 1W to 3W in 0815, 1206, and 2512 chip size

A48 sc70

Abstract: FSC20010035 LMV301 LMV321 LMV821 SC70-5 SC70-5L LMV301MGX
Contextual Info: LMV301 Low Input Bias Current, Single Op Amp Qualification Package National’s LMV301–Low Power, Low Voltage, Single Op Amp Delivers RR/O in a Space Saving SC70 Package IBIAS Current vs. VCM 5 VS =5V 4 IBIAS pA - • Low Input Bias Current (0.18 pA Typ.)

Contextual Info: JkMCC M IC RO POW ER ST A N D A R D C E L L 3.3V / 5V TIMING VERNIERS Timing Vernier cells with outstanding performance characteristics are available for the Micropower fam­ ily. These parametrics have been achieved by com­ bining AM C C 's te ch n ica l expertise w ith a

lm6642

Abstract: NATIONAL SEMICONDUCTOR MARKING CODE 277 marking code 604 SOT23-6 sumitomo epoxy Nitto UV MARKING 5501 SOT23-5 sot23-6 marking code 593 nitto UV tape NS Package Number MF05A operational amplifier discrete schematic
Contextual Info: LMH Products Qualification Package LMH6642, LMH6643, LMH6645, LMH6646, LMH6647, LMH6654, LMH6655 and LMH6672 National's LMH66xx family of operational amplifiers is a new series of high-speed products based on the VIP10 process. The first members of the

Contextual Info: Automotive Grade Ceramic Chip Capacitors NMA Series FEATURES • MANUFACTURED AT ISO/TS 16949 PRODUCTION FACILITY • AEC-Q200 QUALIFIED • SURFACE MOUNT CASE SIZES 0402, 0603, 0805 & 1206 • AVAILABLE IN NPO & X7R DIELECTRICS • AVAILABLE WITH FLEX TERMINATIONS & OPEN MODE

MLCC CRACK

Abstract: specification CECC 32100 AN0010 60068-2-21 Syfer Capacitors
Contextual Info: Syfer Technology Limited, Old Stoke Road, Arminghall, Norwich, Norfolk, NR14 8SQ, United Kingdom Tel: +44 0 1603 723300. Tel. (Sales): 01603 723310 Fax: +44 (0) 1603 723301 Email: sales@syfer.co.uk Web: www.syfer.com The Effect of Lead Free Soldering on

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

Contextual Info: LIE D AP PL IED MICRO C I R C U I T S DfiûTÜDe 0 0 0 1 BD 4 T71 « A f l C C ADVANCE INFORMATION Q20P001 ECL/TTL “TURBO” LOGIC ARRAY with PHASELOCKED LOOP FEATURES • Phase-Locked Loop On-Chip High Frequency Phase-Locked Loop r t : with external filter

Contextual Info: ESD-SAFETM MLC Chips ESD Withstanding Automotive Ceramic Capacitor The ESD-SafeTM series is an enhanced MLC capacitor developed and designed specifically for general ESD protection. ESD = Electro Static Discharge . ESD-SafeTM capacitors are utilized for ESD protection of I/O gates. ESD

AEC-Q200-002

Abstract: RFLW5N1500
Contextual Info: V i s h ay I n t e r t e c h n o l o g y, I n c . Inductors - Wire Bondable, Spiral for RF Circuits I INNOVAT AND TEC O L OGY RFLW N HN RF INDUCTOR O 19 62-2012 Vishay Electro-Films Wire Bondable RF Spiral Inductor Key Benefits • • • • • • •

Contextual Info: ESD-SAFETM MLC Chips ESD Withstanding Automotive Ceramic Capacitor The ESD-SafeTM series is an enhanced MLC capacitor developed and designed specifically for general ESD protection. ESD = Electro Static Discharge . ESD-SafeTM capacitors are utilized for ESD protection of I/O gates. ESD

Contextual Info: Automotive Grade Ceramic Chip Capacitors NMA Series FEATURES • MANUFACTURED AT ISO/TS 16949 PRODUCTION FACILITY • AEC-Q200 QUALIFIED • SURFACE MOUNT CASE SIZES 0402, 0603, 0805 & 1206 • AVAILABLE IN NPO & X7R DIELECTRICS • AVAILABLE WITH FLEX TERMINATIONS & OPEN MODE