PD01S Search Results

Contextual Info: >4MCC Q20000 "T U R B O ECL/TTL TIMING VERNIERS TIMING VERNIER PD01S Figure 16. Functional Block Diagram The PD01S is a programmable delay macro in the Q20000 TU R B O ” family that provides a timing genera­ tion or deskew function for precision timing applications

Contextual Info: PD01S/D series 1W DC/DC CONVERTER, SIP-Package, High Isolation FEATURES Š Efficiency up to 81% Š SIP Package with Industry Standard Pinout Š Package Dimension: 5V&12V Models: 19.5 x 10.2 x 6.1 mm 0.77”x 0.4”x 0.24” 15V&24V Models: 19.5 x 10.2 x 7.1 mm (0.77”x 0.4”x 0.28”)

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability