ECL 81 Search Results

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

SG86A

Abstract: SG53A sg72a LVEP17 MC100ELxxx EP809 LVEL40 SLVS TR30 AND8020
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than

mb 3712

Contextual Info: SK10/100EL91W Triple PECL to ECL/LVECL and LVPECL to ECL/LVECL Translator HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL91W is a triple PECL to ECL/LVECL and LVPECL to ECL/LVECL translator. It is fully compatible with MC100EL91 and MC100LVEL91. The

H604

Abstract: MC100H604 MC100H604FN MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL

PLCC-28

Abstract: H604 MC100H604 MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock

EL91W

Abstract: 597v
Contextual Info: SK10/100EL91W Triple PECL to ECL/LVECL and LVPECL to ECL/LVECL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL91W is a triple PECL to ECL/LVECL and LVPECL to ECL/LVECL translator. It is fully compatible with MC100EL91 and MC100LVEL91. The

H604

Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock

Contextual Info: SPST ECL Switches With Drivers 2662 Series V2.00 Features ● ● ● Broadband Frequency Ranges Environmentally Sealed ECL Compatible Description M/A-COM’s Emitter Coupled Logic ECL PIN diode switches offer multi-octave bands from UHF to Ku-band. Advantages of an ECL switch are narrow pulse width

motorola 305

Abstract: MOTOROLA ecl DL122 H604 MC100H604 MC10H604
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Registered Hex TTL/ECL MC10H604 Translator MC100H604 The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock input. The

CY101E383

Abstract: E383 E1472
Contextual Info: fax id: 5000 i , *" : :V:V:V:V:V:g:-v- : : ^ :^ ; ^3»* i ; : M m : M : i : m : CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpQ TTL-to-ECL — 4 ns tpQ ECL-to-TTL

5D6 diode

Abstract: Power PQFP 64 10e383 Q809
Contextual Info: CY10E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpj) TTL-to-ECL — 3.5 ns tpj) ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply

Contextual Info: CY10E383 CY101E383 CYPRESS SEMICONDUCTOR ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpu TTL-to-ECL — 3.5 ns tpu ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply

10H645

Abstract: E211 MC10E111 MPC973 AN1405
Contextual Info: AN1405/D ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides information on system design using ECL logic technologies for reducing system clock skew over

E383

Abstract: all ttl family not ecl quad single supply 50 Ohm Line Drivers TTL LOGIC DATA BOOK CY101E383 R2170 E3836 E3834 E3831
Contextual Info: fax id: 5000 1CY 101 E3 83 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL • • • • • • • • • • — 4 ns tPD ECL-to-TTL Low skew < ± 1 ns

10H645

Abstract: AN1405 E211 MC10E111 MPC973
Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

10H645

Abstract: AN1405 DL140 E211 MC10E111 MPC973
Contextual Info: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL

ecl 84

Abstract: ecl not CY101E383 R2170
Contextual Info: CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL • • • • • • • • • • — 4 ns tPD ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply

LVEL91

Abstract: DL140 MC100EL91 MC100LVEL91 SE540 Nippon capacitors
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard

Contextual Info: MOTOROLA Order this document by MC100EP90/D SEMICONDUCTOR TECHNICAL DATA Product Preview MC100EP90 Triple ECL to PECL Translator The MC100EP90 is a TRIPLE ECL TO PECL translator. The device receives Low Voltage differential ECL signals and translates them to Low

CY101E383

Abstract: E383 99s1
Contextual Info: fax id: 5000 ,.V.Ï.Ï.V.^ y nr' Æ C Y 101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpQ TTL-to-ECL — 3 ns tpQ ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply

Contextual Info: fax id: 5000 «f C Y 101E383 c y pr es s ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpD TTL-to-ECL — 4 ns tpD ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply

signal path designer

Contextual Info: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability

KLT25

Abstract: HLT25 mst 720 ELT25 MC100ELT25 MC10ELT25
Contextual Info: MC10ELT25, MC100ELT25 Differential ECL to TTL Translator The MC10ELT/100ELT25 is a differential ECL to TTL translator. Because ECL levels are used a +5V, -5.2V or -4.5V and ground are required. The small outline 8-lead SOIC package and the single gate of

MC100EP90

Abstract: MC10EP90
Contextual Info: MC10EP90, MC100EP90 −3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator Description The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.