LVEL91 Search Results

MC100EL91

Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16 100H646
Contextual Info: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE WIRE BONDED Device Failure Mechanisms For the plastic DIP, SOIC, TSSOP, PLCC, TQFP, and

MC100EL92

Abstract: AN1560 EL90 SWITCH XCJC AN1503 DL140 LVEL11 LVEL16 motorola LOGIC
Contextual Info: AN1560 Application Note Low Voltage ECLinPS SPICE Modeling Kit Prepared by Cleon Petty Motorola Logic Applications Engineering ECLinPS and ECLinPS Lite are trademarks of Motorola, Inc. 6/97  Motorola, Inc. 1997 1 REV 1 AN1560 Low Voltage ECLinPS SPICE Modeling Kit

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

AN1406

Abstract: AN1568 DL140 MC100EL17 MC100LVEL29 MC100LVEL39 P1596 lvds positive negative
Contextual Info: AN1568 Application Note Interfacing Between LVDS and ECL Revised by Paul Shockman Motorola Applications Engineering 2/99  Motorola, Inc. 1999 5–1 REV 1 AN1568 Interfacing Between LVDS and ECL specifications, the general purpose specification with 250 to

Contextual Info: LVEL91 3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator Description The LVEL91 is a triple LVPECL input to ECL output translator. The device receives low voltage differential PECL signals, determined by the VCC supply level, and translates them to differential

AN1568

Abstract: DL140 MC100EL17 MC100LVEL17 MC100LVEL39 MC100LVEL90 P1596 DL140-D Nippon capacitors
Contextual Info: AN1568 Application Note Interfacing Between LVDS and ECL Prepared by Andrea Diermeier Motorola Logic Engineering 5/96  Motorola, Inc. 1996 5–1 REV 0 AN1568 Interfacing Between LVDS and ECL Introduction LVDS Levels LVDS Low Voltage Differential Signaling signals are

MC100EL91

Abstract: MC100LVEL91 MC100LVEL91DW MC100LVEL91DWR2
Contextual Info: LVEL91 3.3V / 5VĄTriple LVPECL / PECL Input to -3.3V ECL Output Translator The LVEL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and

MC100EL91

Abstract: MC100LVEL91 MC100LVEL91DW MC100LVEL91DWR2
Contextual Info: LVEL91 3.3V / 5VĄTriple LVPECL / PECL Input to -3.3V ECL Output Translator The LVEL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and

3335

Abstract: MC100EL91 MC100EPT25 MC100LVEP16 MC10LVEP16
Contextual Info: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE WIRE BONDED Device Failure Mechanisms For the plastic DIP, SOIC, TSSOP, PLCC, TQFP, and

K1213

Abstract: k1518 transistor c1213 equivalent transistor k1213 k1112 K1113 k0305 k0205 k0309 equivalent k1117
Contextual Info: AN1560/D Low Voltage ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora and Paul Shockman ON Semiconductor Broadband Application Engineers http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to extend the information given

AN1406

Abstract: MC100LVEL13 MC100LVEL14 MC100LVEL17 MC100LVEL29 P1596 AN1568
Contextual Info: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Shockman Logic Applications Engineering http://onsemi.com APPLICATION NOTE LVDS outputs require a 100 Ω load between the differential outputs. This load will in addition terminate the 50 Ω controlled impedance lines.

MC100EL91

Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16
Contextual Info: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE WIRE BONDED Device Failure Mechanisms For the plastic DIP, SOIC, TSSOP, PLCC, TQFP, and

100LVEL91

Abstract: MC100EL91 MC100LVEL91 MC100LVEL91DW MC100LVEL91DWR2
Contextual Info: LVEL91 3.3V / 5VĄTriple LVPECL / PECL Input to -3.3V ECL Output Translator The LVEL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator LVEL91 MC100EL91 The MC100LVEL/EL91 is a triple PECL to ECL translator. The LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard

MC100EL91

Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16 E1651
Contextual Info: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE INTRODUCTION Normal operation of Integrated Circuits will cause electrical power, P, to be converted into heat by the die

EL-7L

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview T riple PECL to ECL T ran slator LVEL91 MC100EL91 The MC100LVEL/EL91 is a triple PECL to ECL translator. The device receives either standard or low vollage differential PECL signals and translates them to either standard or low voltage differential ECL output

MC100EL91

Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16
Contextual Info: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE INTRODUCTION Normal operation of Integrated Circuits will cause electrical power, P, to be converted into heat by the die

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA P roduct Preview LVEL91 MC100EL91 Triple PECL to ECL Translator The MC100LVEL/EL91 is a triple PECL to ECL translator. The device receives either standard or low voltage differential PECL signals and translates them to either standard or low voltage differential ECL output

el90

Abstract: H352 DL122 DL140 ept20 EPT25 LVEL92 EPT22 H124 ttl databook
Contextual Info: AN1672/D The ECL Translator Guide ECL • TTL • PECL • LVECL • LVPECL • CMOS • LVTTL How To Make Them Talk To Each Other http://onsemi.com Prepared by: Paul Shockman, Paul Hunt ON Semiconductor Logic Applications Engineering APPLICATION NOTE Translation between ECL signals off different power

Contextual Info: LVEL91 3.3 V Triple LVPECL Input to −3.3 V to −5.0 V ECL Output Translator The LVEL91 is a triple LVPECL input to ECL output translator. The device receives low voltage differential PECL signals, determined by the VCC supply level, and translates them to differential

H124

Abstract: LVEL17 MC10EPT20
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering APPLICATION NOTE Objective This application note is intended to provide the basic device selection and connection information to enable signal

k1213

Abstract: transistors k2628 transistor c1213 equivalent k1317 K0316 k2225 transistor k0232 k1117 k1518 k0317
Contextual Info: AN1560/D Low Voltage ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora and Paul Shockman ON Semiconductor Broadband Application Engineers http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to extend the information given

MC10EPT25

Abstract: MC10EPT22 MC10EPT24 MC10EPT23 MC10EPT21 ttl 7709 AND8072 HCT CMOS family characteristics AN1568 AND8020
Contextual Info: AN1672/D The ECL Translator Guide PECL • LVPECL • NECL • TTL • LVTTL/LVCMOS • CMOS http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Objective receiver in the LOW state. In contrast, ECL drivers source current in both HIGH and LOW states to the receiver).

k2225 transistor

Abstract: k1118 k1117 k1213 power transistor k1821 transistor k1213 k1117 transistor K2225 k1518 transistor k1117
Contextual Info: AN1560/D Low Voltage ECLinPS and ECLinPS Lite SPICE Modeling Kit 150Prepared by Senad Lomigora and Paul Shockman ON Semiconductor Broadband Application Engineers http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to extend the information given