ECL 100K Search Results

Contextual Info: bel ACTIVE DELAY LINES cont. Style ECL ECt ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10K H 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap 10KH 5 Tap ECL ECL ECL ECL ECL ECL

ecl 10K

Abstract: e103 resistor 603 dip ECL-10K E1001 series ecl10k
Contextual Info: ECL DIGITAL DELAY LINES SERIES E10 - ECL 10K INTERFACED SERIES E100 - ECL 100K INTERFACED TEST CONDITIONS @25°C • ■ ■ ■ ■ ■ Industry’s widest selection! Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

100K series ECL

Abstract: ECL-10K
Contextual Info: ECL DIGITAL DELAY LINES SERIES E10 - ECL 10K INTERFACED SERIES E100 - ECL 100K INTERFACED TEST CONDITIONS @25°C • ■ ■ ■ ■ ■ Industry’s widest selection! Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin D IP on ECL 10K, 24 pin DIP on ECL 100K

Contextual Info: ECL DIGITAL DELAY LINES SERIES E10 - ECL 10K INTERFACED SERIES E100 - ECL 100K INTERFACED TEST CONDITIONS @25°C • ■ ■ ■ ■ ■ Industry’s widest selection! Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

Contextual Info: ECL DIGITAL DELAY LINES SERIES E10 - ECL 10K INTERFACED SERIES E100 - ECL 100K INTERFACED TEST CONDITIONS @25°C • ■ ■ ■ ■ ■ Industry’s widest selection! Economical cost, prom pt delivery Fast 2nSec rise tim e typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

ecl 10K

Abstract: RCD Components E1001 E1004 E1008 E103 E105 SCHEMAT
Contextual Info: PRELIMINARY ECL DIGITAL DELAY LINES -5-41-5 - ECL 10K INTERFACED -5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay nS 3 20 4 25 5 30 6 2X Total Delay Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate

Contextual Info: TIEPAL10016ET6C ECL-TO-TTLIMPACT-X" PAL TRANSLATOR CIRCUIT D3352, OCTOBER 1989 • ECL 100K Programmable Logic with ECL-to-TTL Translation JT PACKAGE TOP VIEW • ECL Control Inputs vcc[ '[ l[ l[ l[ l[ '[ '[ • 3-State TTL Outputs • IMPACT-X“ Process with Reliable

Contextual Info: MC10H604 MC100H604 MOTOROLA Product Preview REGISTERED HEX TTL TO ECL TRANSLATOR Registered Hex TTL/ECL Translator The MC1 OH/100H604 is a 6-bit, registered, dual supply TTL to ECL translator. The de­ vice features differential ECL outputs as well as a choice between either a differential ECL

Contextual Info: ECL DIGITAL DELAY LINES RESISTORS •CAPS » COILS •DELAY U NES E10 SERIES - ECL10KINTERFACED E100 SERIES - ECL 100K INTERFACED FEATURES □ Industry’s widest selection! □ Economical cost, prompt delivery □ Fast 2nSec rise time typical □ Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

d2981

Abstract: CY101E383 E383 coaxial d8
Contextual Info: CY101E383 ECL/TTL/ECL Translator and HighĆSpeed Bus Driver Features D D tors. The part meets standard 100K logic BiCMOS for optimum speed/power The a newĆgeneration dent TTL ĆtoĆECL and ten independent Low skew < ± 1 ns ECL ĆtoĆTTL translators for ECL and TTL power/ground pins to reĆ

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

b765

Abstract: PAL 008 PAL10016RD8 PAL1016RD8
Contextual Info: PRELIMINARY September 1986 ECL Registered and Latched Programmable Array Logic PAL Family General Description The registered and latched ECL PAL devices are the latest additions to National Semiconductor's ECL PAL family. The ECL PAL family utilizes National Semiconductor's advanced

mb 3712

Contextual Info: SK10/100EL91W Triple PECL to ECL/LVECL and LVPECL to ECL/LVECL Translator HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL91W is a triple PECL to ECL/LVECL and LVPECL to ECL/LVECL translator. It is fully compatible with MC100EL91 and MC100LVEL91. The

signal path designer

Contextual Info: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability

XEP56V

Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle

100K series ECL

Contextual Info: ECL DIGITAL DELAY LINES E10 SERIES - ECL10K INTERFACED E100 SERIES - ECL100K INTERFACED Industry’s widest selection! 5nS - 200nS 500nS avail. Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

H604

Abstract: MC100H604 MC100H604FN MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL

PLCC-28

Abstract: H604 MC100H604 MC10H604 MC10H604FN
Contextual Info: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock

XEP57V

Abstract: marking k4 XEP57
Contextual Info: ECL Pro 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel ECL Pro™ SY100EP57V SY100EP57V FINAL FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time

mb 3712

Abstract: MC100EL91 MC100LVEL91 SK100EL91WD SK100EL91WDT SK10EL91WD SK10EL91WDT un 1950
Contextual Info: SK10/100EL91W Triple PECL to ECL/LVECL and LVPECL to ECL/LVECL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL91W is a triple PECL to ECL/LVECL and LVPECL to ECL/LVECL translator. It is fully compatible with MC100EL91 and MC100LVEL91. The

EL563-2

Abstract: L553 z8.2 EL553-2
Contextual Info: DATATRONICS D • SbSlMÔS DOOOEbb 1 ■ SERIES EL553 ECL 100K COMPATIBLE PROGRAMMABLE DELAY MODULES (4-BIT) ( • • ECL 100K Input and Output Levels »24-pin D IL Package All Delays Digitally Programmable • 70 ECL DC Fan-out Capacity Specifications:

MC10EP58D

Abstract: MC10EP58DR2 SY100EP58V SY10EP58V SY10EP58VZI SY10EP58VZITR
Contextual Info: ECL Pro SY10EP58V ECL Pro™ SY100EP58V 3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER Micrel, Inc. SY10EP58V SY100EP58V FEATURES • 2:1 PECL/ECL multiplexer ■ Guaranteed AC–performance over temperature/voltage • >3GHz fMAX toggle • <200ps rise/fall time

Contextual Info: ECL DIGITAL DELAY LINES E10 SERIES - ECL10K INTERFACED E100 SERIES - ECL100K INTERFACED Industry’s widest selection! 5nS - 200nS 500nS avail. Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

ecl pal

Contextual Info: ECL PAL10/10016RD8 National iD I Semiconductor PAL10/10016RD8 ECL Registered Programmable Array Logic General Description The registered ECL PAL10/10016RD8 is offered in 10KH or 100K compatible versions. A maximum propagation delay of 6 ns input to output characterizes the performance of this