ECL100K Search Results

Contextual Info: lowprofile ECL100K COMPATIBLE LOGIC DELAY MODULE # # # # # # ECL 100K in put and outputs Delays stable and precise 24-pin DIP package .375 high Available in delays fro m 16 to 80ns 12.5% taps — each isolated and w ith 70 ECL DC fan-out capacity Fast rise tim e on all outputs

Contextual Info: ECL100K COMPATIBLE 4-BIT RAMMABLE DELAY LINE ECL 100K input and output levels Delays stable and precise 24-pin DIP package .375 high The Available in delays up to 77.8ns Logic Delay Lines are digitally programmable by the presence of either a " 1 " or a " 0 " at each o f the programming

Contextual Info: ECL100K COMPATIBLE 4-BIT PROGRAMMABLE LOGIC DELAY LINE # E C L 1 0 0 K in p u t and o u tp u t levels # Delays stable and precise # 24-pin D IP package .3 7 5 high # A vailable in delays up to 77.8ns # A vailable in 18 delay steps w ith resolution The fro m 0.1 to 5.0ns

ecl100

Contextual Info: very lewprofile ECL100K COMPATIBLE LOGIC DELAY MODULE 100K ECL input and outputs The 10 0 K ECL LDM is offered in nineteen 1 9 delays from 9ns Delays stable and precise to 80 n s , w ith each module incorporating taps at 1 2 .5 % 24-pin DIP package (.3 0 0 high)

Contextual Info: ECL DIGITAL DELAY LINES E10 SERIES - ECL10K INTERFACED E100 SERIES - ECL100K INTERFACED Industry’s widest selection! 5nS - 200nS 500nS avail. Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

Contextual Info: GEC PLESSEY [ s e m i c o n d u c t o r s PRELIMINARY INFORMATION 1 SP2001 100MHz DIRECT DIGITAL FREQUENCY SYNTHESISER Supersedes January 1991 Edition The SP2001 Direct Frequency Synthesiser (DFS) is an ECL100K compatible ‘numerically controlled oscillator' i.e. it

Contextual Info: lawprofile ECL100K COMFATIBLE LOGIC DELAY MODULE # # # # # ECL 100K input and outputs Delays stable and precise 24-pin D IP package .375 high Available in delays from 16 to 80ns 12.5% taps — each isolated and with 70 ECL DC fan-out capacity Fast rise tim e on all outputs

Contextual Info: GEC PLESSEY 1 S E M I C O N D U C T O R~S~] PRELIMINARY INFORMATION SP2001 100MHz DIRECT DIGITAL FREQUENCY SYNTHESISER Supersedes January 1991 Edition The SP2001 Direct Frequency Synthesiser (DFS) is an ECL100K compatible 'numerically controlled oscillator' i.e. it

BPECLDL-4.5-0.2

Abstract: ECL100K
Contextual Info: ECL100K COMPATIBLE 8-BIT BINARY/ DECADE PROGRAMMABLE LOGIC DELAY LINE # ECL 1 00 K in p u t and o u tp u t levels # Delays stable and precise # 3 4-pin DIP package .3 7 5 high # A vaila ble in delays up to 1 3 2 n s # A vaila ble in Binary and Decade versions

Contextual Info: lowprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # E C L 1 0 0 K in p u t and o u tp u t levels # D ual units w ith separate trigger inputs and panying outputs C onditions" shown. Pulse w id th s stable and precise on both leading and trailing edge.

100K series ECL

Contextual Info: ECL DIGITAL DELAY LINES E10 SERIES - ECL10K INTERFACED E100 SERIES - ECL100K INTERFACED Industry’s widest selection! 5nS - 200nS 500nS avail. Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

ECL100K

Abstract: digital frequency multiplier
Contextual Info: lowprofile ECL100K COMPATIBLE DIGITAL FREQUENCY MULTIPLIER MODULE The EC L-100K -D FM M is offered in twenty-six 261 standard # ECL 1 0 0 K input and o utput levels # O utput w avetrain synchronized clock frequencies from 50 to 250 Mhz. W hen tested under the

Contextual Info: 2.5Gb/s GaAs 1:16 Demultiplexer 1C FMM4007KC-1 FEATURES • • • • • High Speed Operation up to 2.5Gbps Low Power Dissipation: 1.4W Typ Single Power Supply: VEE = -5.2V High Speed Differential I/O: 2.5GHz clock inputs ECL100K Compatible Parallel data I/O: Single-Ended 155Mbps parallel

demultiplexer ic

Contextual Info: 2.5Gb/s GaAs 1:16 Demultiplexer IC FMM4007KC-1 FEATURES • • • • • High Speed Operation up to 2.5Gbps Low Power Dissipation: 1.4W Typ Single Power Supply: VEE = -5.2V High Speed Differential I/O: 2.5GHz clock inputs ECL100K Compatible Parallel data I/O: Single-Ended 155Mbps parallel

Demultiplexer IC

Abstract: ECL100K FMM4007KC-1 1 into 16 demultiplexer circuit diagram CLK16N
Contextual Info: 2.5Gb/s GaAs 1:16 Demultiplexer IC FMM4007KC-1 FEATURES • • • • • High Speed Operation up to 2.5Gbps Low Power Dissipation: 1.4W Typ Single Power Supply: VEE = -5.2V High Speed Differential I/O: 2.5GHz clock inputs ECL100K Compatible Parallel data I/O: Single-Ended 155Mbps parallel

Contextual Info: ECL100K COMPATIBLE RAMMABLE DELAY LINE ECL 10OK input and output levels Delay programming is accomplished in two decades using standard BC D code 1-2-4-8 on eight programming lines. The 100 picosecond steps are controlled by inputs to terminals P1, P2, P3 and P4 with P1 being the least significant bit. The 1

022080

Abstract: DECLPGM-2-10 ECL100K
Contextual Info: ENGI N E E R E D COMPONENTS CO 7 3 »e J 33335ñ3 ODGOSSS 7 "F S H *! hwprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # # # # # # # ECL 100K input and output levels Dual units with separate trigger inputs and outputs Pulse widths stable and precise

Contextual Info: ECL100K COMPATIBLE 8-BIT BINARY/ DECADE PROGRAMMABLE LOGIC DELAY LINE EC L 100K input and output levels Delays stable and precise 34-pin DIP package .375 high Available in delays up to 132ns Available in Binary and Decade versions Step resolution from 0.1 to 0.5ns

Contextual Info: ENGI N E E R E D COMPONENTS CO 7 3 »e J 33335ñ3 ODGOSSS 7 "F S H *! hwprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # # # # # # # ECL 100K input and output levels Dual units with separate trigger inputs and outputs Pulse widths stable and precise

Contextual Info: verylewprofile ECL100K COMPATIBLE LOGIC DELAY MODULE # 100K E C L input and outputs Delays stable and precise 24-pin DIP package .300 high Available in delays from 9 to 80ns 1 2 .5 % taps—each isolated and with 70 ECL DC fan-out capacity Fast rise time on all outputs

ic LK 1628

Contextual Info: FMM4007KC Ga As 2.5Gbps 1:16 Demultiplexer 1C FEATURES • • • • • High Speed Operation up to 2.5Gbps Low Power Dissipation: 1.4W Typ Single Power Supply: VEE = -5.2V High Speed Differential I/O: 2.5GHz clock inputs ECL100K Compatible Parallel data I/O: Single-Ended 155Mbps parallel

ecl 806

Abstract: 100K-ECL-LDM-40 ky 202 h 100K-ECL-LDM-16 ECL100K
Contextual Info: wry lowprofile ECL100K COMPATIBLE LOGIC DELAY MODULE _ j # 1 0 0 K ECL in p u t and o u tp u ts # D elays sta b le and precise + 2 4 -p in DIP package .3 0 0 high # A v a ila b le in delays fro m 9 to 8 0 n s # 1 2 .5 % ta p s — each isola ted and w ith

Contextual Info: lowprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # # # # % # # ECL 100K input and output levels Dual units with separate trigger inputs and outputs Pulse widths stable and precise 12-pin DIP package .325 high Available in pulse widths from 2ns to 50ns

Contextual Info: lowprofile ECL100K COMPATIBLE LOGIC DELAY MODULE # ECL 100K input and outputs # Delays stable and precise # 24-pin DIP package .375 high w ith each m o d ule in c o rp o ra tin g taps at 1 2 .5 % increm ents o f to ta l # Available in delays from 16 to 80ns