DQS_ Search Results

NT5TU128M8DE

Abstract: NT5TU64M16DG nt5tu64m16dg-Bd NT5TU128M8DE-BD NT5TU256M4DE nt5tu64m NT5TU64M16 NT5TU64M16DG-3C NT5TU64M16DG-3CI NT5TU64M16DG-BE
Contextual Info: NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG NT5TB256M4DE / NT5TB128M8DE / NT5TB64M16DG 1Gb DDR2 SDRAM Feature CAS Latency Frequency -37B/-37BI -3C/-3CI -AD/-ADI -AC/-ACI/-ACL -BE -BD DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 DDR2-1066 4-4-4 5-5-5 6-6-6

nt5tu128m8de-ac

Abstract: NT5TU64M16DG-AD NT5TU128M8DE-AD NT5TU256M4DE NT5TU128M8DE NT5TU64M16DG NT5TU64M16DG-3C Nanya NT5TU64M16DG
Contextual Info: NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG 1Gb DDR2 SDRAM Preliminary Edition Features CAS Latency and Frequency Speed Sorts -37B DDR2 -533 -3C DDR2 -667 -AD DDR2 -800 -AC DDR2 -800 Units Bin CL-tRCD-TRP 4-4-4 5-5-5 6-6-6 5-5-5 tck max. Clock Frequency 266

NT5TU32M16AG-37B

Abstract: NT5TU128M4AE nt5tu64m8 nt5tu64m NT5TU32M16 NT5T nt5tu32m16ag nt5tu64m8af
Contextual Info: NT5TU128M4AB/NT5TU128M4AE Green NT5TU64M8AF/NT5TU64M8AB/NT5TU64M8AE(Green) ) 512Mb DDR2 SDRAM Features • Write Latency = Read Latency -1 CAS Latency and Frequency • Programmable Burst Length: 4 and 8

NT5TU32M16CG-BD

Abstract: NT5TU32M16CG-be NT5TU64M8CE
Contextual Info: NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG 512Mb DDR2 SDRAM C-Die Features • 1.8V ± 0.1V Power Supply Voltage • Data-Strobes: Bidirectional, Differential • Programmable CAS Latency: 3,4,5,6 and 7 • 4 internal memory banks • Programmable Additive Latency: 0, 1, 2, 3, and 4

ARM926EJS

Abstract: ARM926EJ-S cdm-9 NAND FLASH Controller i2s1tx_clk
Contextual Info: LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01 — 6 February 2009 Preliminary data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high

TAG 8926

Abstract: Lpg 899 SDC 2921 TF 6221 HEN LED display 12V+RELAY+1+C/8 pin ic sdc 3733
Contextual Info: MCIMX31 and MCIMX31L Multimedia Applications Processors Reference Manual MCIMX31RM Rev. 1 2/2006 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130

OC48

Abstract: SSTL-15 SSTL-18
Contextual Info: Arria II Device Handbook Volume 3: Device Datasheet and Addendum Arria II Device Handbook Volume 3: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-4.0 Document last updated for Altera Complete Design Suite version:

W971GG6JB

Abstract: 8X12 DDR2-667 DDR2-800 0A80
Contextual Info: W971GG6JB 8M  8 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

e500v2

Abstract: MPC8544 JTAG connector Samsung Nexus S samsung emcp ordering information NV 15F PCI express PCB footprint MSC8101 TLC 1298 SRam program 61256 apple crypto
Contextual Info: MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual Supports MPC8544E MPC8544 MPC8544ERM Rev. 1 10/2007 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed:

socket am3 pinout

Abstract: socket AM2 pinout AM2 pinout Socket F am2 socket pin diagram am3 socket pinout am3 socket pin diagram am2 socket pinout socket AM3 pinout diagram PCIe cable pinout LX5511
Contextual Info: Broaddown4 User Manual Issue – 2.00 draft Enterpoint Ltd. - Broaddown4 Manual – Issue 2.00 11/04/2007 Kit Contents You should receive the following items with you Broaddown4 development kit: 1 - Broaddown4 Board 2 - Programming Cable Prog2 Figure 1 - Broaddown4 Board

transistor b1240

Abstract: B1240 transistor B1240 r DDR333 PAR64 PC2700 REQ64
Contextual Info: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data

Contextual Info: External Memory Interfaces in Stratix V Devices 7 2012.12.28 SV51008 Subscribe Feedback The Stratix V devices provide an efficient architecture that allows you to fit wide external memory interfaces to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are

400B

Abstract: DDR2-400 DDR2-533 DDR667 HYB18T512 HYB18T512160AF HYB18T512400AF HYB18T512800AF HYB18T512400AF5
Contextual Info: D a t a S he et , Rev. 1.3, J a n. 2 00 5 HYB18T512400AF HYB18T512800AF HYB18T512160AF 512-Mbit DDR2 SDRAM DDR2 SDRAM RoHS Compliant Products M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . Edition 2005-01 Published by Infineon Technologies AG,

PPC405D4

Abstract: IBM powerpc 405gp NP4GS3 PVA c17 13n07 LP1 K09 marking a00b TDA 2040 XC5 539 405GP
Contextual Info:  IBM PowerNP NP2G Network Processor Preliminary February 12, 2003  0.1 Copyright and Disclaimer  Copyright International Business Machines Corporation 2003 All Rights Reserved US Government Users Restricted Rights - Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp.

Contextual Info: W631GU6KB 8M  8 BANKS  16 BIT DDR3L SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

NT5CB64M16AP-CF

Abstract: nt5cb64m16 NT5CB64M16AP-CG NT5CB64M16AP nanya NT5CB64M16AP NT5CB64m NT5CB64M16AP-BE nt5cb64m16ap-dh MPR 20 20 CF RESISTOR NT5CB64M16AP-AC
Contextual Info: 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature  Write Leveling  1.5V ± 0.075V JEDEC Standard Power Supply  OCD Calibration  8 Internal memory banks (BA0- BA2)  Dynamic ODT (Rtt_Nom & Rtt_WR)  Differential clock input (CK, )

NT5TU256T8DY

Abstract: 128 MB DDR2 SDRAM DDR2-667 DDR2-800 NT5TU256T8DY-3C
Contextual Info: NT5TU512T4DY / NT5TU256T8DY 2Gb DDR2 SDRAM DDP Features • Programmable Additive Latency: 0, 1, 2, 3 and 4 CAS Latency and Frequency Speed Sorts DDR2-667 DDR2-800 DDR2-800 (-3C) (-AC) (-AD) Bin • Write Latency = Read Latency -1 Units • Programmable Burst Length: 4 and 8

NT5TU64M16

Abstract: NT5TU128M8BJ-3C NT5TU64M16BM nt5tu64m NT5TU128M8 128 MB DDR2 SDRAM 1GB DDR2 4 banks NT5TU256M4BJ
Contextual Info: NT5TU256M4BJ / NT5TU128M8BJ / NT5TU64M16BM Green 1Gb DDR2 SDRAM Features CAS Latency and Frequency Speed Sorts -5A DDR2 -400 -37B DDR2 -533 -3C DDR2 -667 -25D DDR2 -800 Units Bin (CL-tRCD-TRP) 3-3-3 4-4-4 5-5-5 6-6-6 tck max. Clock Frequency 200 266 333 400

W631GG6KB-12

Abstract: W631GG6KB-15 W631GG6KB15A DDR3 DIMM SPD JEDEC 24si 9x13 W631GG6KB15K w631gg6k W631GG6KB12I W631GG6KB-15I
Contextual Info: W631GG6KB 8M  8 BANKS  16 BIT DDR3 SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

Contextual Info: W9712G6KB 2M  4 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

W971GG6KB

Abstract: W971GG6KB-3 W971GG6KB-25 W971GG6KB25
Contextual Info: W971GG6KB 8M  8 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

LCMXO2-1200HC-4TG100C

Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
Contextual Info: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1

sandisk eMMC 4.41

Abstract: toshiba emmc 4.4 spec SANDISK inand Samsung eMMC 4.41 sandisk emmc 4.5 bcm 4330 programming Guide Sandisk iNAND eMMC toshiba emmc 4.4 linux toshiba emmc 4.4.1 spec sandisk inand extreme emmc
Contextual Info: An addendum for this document is available. See Document ID#: IMX25RMAD. i.MX25 Multimedia Applications Processor Reference Manual Supports i.MX251 MCIMX251 i.MX253 (MCIMX253) i.MX255 (MCIMX255) i.MX257 (MCIMX257) i.MX258 (MCIMX258) IMX25RM Rev. 1 06/2009

TN1178

Abstract: DDR3 DIMM footprint LVCMOS15 LVCMOS25 LVCMOS33 SSTL15D k2xsc
Contextual Info: LatticeECP3 High-Speed I/O Interface June 2010 Technical Note TN1180 Introduction LatticeECP3 devices support high-speed I/O interfaces, including Double Data Rate DDR and Single Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one