DQPA Search Results

AS5SS256K18

Contextual Info: SSRAM Austin Semiconductor, Inc. 256K x 18 SSRAM PIN ASSIGNMENT Top View Synchronous Burst SRAM, Flow-Through SA SA CE\ CE2 NC MARKING -8* -9 -10 SA NC NC VDDQ V SS NC DQPa DQa DQa V SS VDDQ DQa DQa V SS NC VDD ZZ DQa DQa VDDQ V SS DQa DQa NC NC V SS VDDQ

7273B

Contextual Info: SSRAM AS5SS256K18 256K x 18 SSRAM PIN ASSIGNMENT Top View Synchronous Burst SRAM, Flow-Through 100-pin TQFP SA SA CE\ CE2 NC NC bwB\ BWa\ CE2\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA SA FEATURES VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC

Contextual Info: SSRAM AS5SS256K36 256K x 36 SSRAM PIN ASSIGNMENT Top View Flow-Through, Synchronous Burst SRAM 100-pin TQFP (DQ, DQC & DQCR) FEATURES              DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss

Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

AS5SP512K36DQ

Contextual Info: SSRAM A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A AS5SP512K36DQ Plastic Encapsulated Microcircuit Symbol tCYC tCD tOE 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 Units ns ns ns 81 84 82 83 85 87 86 89 88

MS-026

Abstract: MT55L256L32P MT55L256L36P MT55L256V32P MT55L256V36P MT55L512L18P MT55L512V18P
Contextual Info: 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM 8Mb ZBT SRAM MT55L512L18P, MT55L512V18P, MT55L256L32P, MT55L256V32P, MT55L256L36P, MT55L256V36P 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • • • • • •

AS7C331MNTD32A

Abstract: AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A
Contextual Info: November 2004 AS7C331MNTD32A AS7C331MNTD36A 3.3V 1M x 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns

K7A323600M

Abstract: K7B321825M-QC65 K7A321800M
Contextual Info: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

MT55L256L18P1T-10A

Abstract: MS-026 MT55L128L32P1 MT55L128L36P1 MT55L128V32P1 MT55L128V36P1 MT55L256L18P1 MT55L256L18P1T-10 MT55L256V18P1 84 FBGA thermal
Contextual Info: PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 4Mb ZBT SRAM MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • •

K7Z327285M

Contextual Info: K7Z327285M Preliminary 512Kx72 DLW Double Late Write RAM Document Title 512Kx72 DLW(Double Late Write) RAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Device name change from Double Late Write SigmaRAM to Double Late Write RAM

MT58L64L36P

Abstract: MS-026 MT58L128L18P MT58L128V18P MT58L64L32P MT58L64V32P MT58L64V36P
Contextual Info: NOT RECOMENDED FOR NEW DESIGNS 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2Mb SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, SingleCycle Deselect FEATURES

K7M321825M

Abstract: K7M321825M-QC75 K7M323625M K7M323625M-QC75
Contextual Info: K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

K7A401800B-QC

Abstract: K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC
Contextual Info: K7A403609B K7A403209B K7A401809B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

K7M643635M-Q

Contextual Info: K7N643631M K7N641831M Preliminary 2Mx36 & 4Mx18 Pipelined NtRAM TM Document Title 2Mx36 & 4Mx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. Sep. 30. 2002 Advance 0.1 1. Delete the speed bins FT : 7.5ns, 8.5ns / PP : 200MHz

K7N401801B

Abstract: K7N403601B
Contextual Info: K7N403601B K7N401801B 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 350mA to 290mA at -16,

K7B801825B

Abstract: K7B803625B
Contextual Info: K7B803625B K7B801825B 256Kx36 & 512Kx18 Synchronous SRAM Document Title 256Kx36 & 512Kx18-Bit Synchronous Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft May. 18 . 2001 Preliminary 0.1 Add x32 org part and industrial temperature part

K7N161801A

Abstract: K7N163601A
Contextual Info: K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM TM Document Title 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Initial document. Add JTAG Scan Order Add x32 org and industrial temperature . Add 165FBGA package Speed bin merge.

IS61LPD51236A

Abstract: IS61LPD102418A IS61VPD102418A IS61VPD51236A
Contextual Info: IS61VPD51236a IS61VPD102418a IS61lPD51236a IS61LPD102418a 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and

Contextual Info: K7A163608A K7A163208A K7A161808A PRELIMINARY 512Kx36/x32 & 1Mx18 Synchronous SRAM Document Title 512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial draft 1. Add x32 org and industrial temperature

CS21

Abstract: KM736V687A KM736V687A-7 KM736V687A-8 KM736V687A-9
Contextual Info: P R E LIM IN A R Y KM736V687A 64Kx36 Synchronous SRAM P o c u M e flL IltJ e 64K x36-Bit S ynchronous Burst SRAM R e visio n H is to ry Rev. No. H isto ry 0.0 Initia l d ra ft 0.1 C h a n g e D C C h a ra c te ris tic s . Ic c v a lu e fro m 3 2 0 m A to 2 5 0 m A

Contextual Info: CY7C1460AV25 CY7C1462AV25 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

K7A161801M

Abstract: K7A163601M advh
Contextual Info: K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM Document Title 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft Jan. 18. 1999 Preliminary 0.1 1. Update ICC & ISB values. 2. Remove tCYC 117MHz -85