CY7C1368C Search Results
CY7C1368C Datasheets (5)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CY7C1368C | Cypress Semiconductor | 9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original | 401.33KB | 18 | ||
| CY7C1368C-166AJXC | Cypress Semiconductor | 9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original | 401.33KB | 18 | ||
| CY7C1368C-166AXC | Cypress Semiconductor | 9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original | 401.33KB | 18 | ||
| CY7C1368C-166AXCT | Cypress Semiconductor | Memory, Integrated Circuits (ICs), IC SRAM 8MBIT 166MHZ 100LQFP | Original | 18 | |||
| CY7C1368C-166AXI | Cypress Semiconductor | 9-Mbit (256K x 32) Pipelined DCD Sync SRAM | Original | 401.32KB | 18 |
CY7C1368C Price and Stock
Cypress Semiconductor CY7C1368C-166AXCCY7C1368C-166AXC |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
CY7C1368C-166AXC | 88 | 34 |
|
Buy Now | ||||||
| CY7C1368C-166AXC | 73 | 34 |
|
Buy Now | |||||||
|
CY7C1368C-166AXC | 1,543 | 1 |
|
Buy Now | ||||||
CY7C1368C Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
|
Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state |
Original |
cy7c1368c | |
|
Contextual Info: CY7C1368C 9-Mbit 256 K x 32 Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM Features Functional Description[1] • Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ❐ Depth expansion without wait state |
Original |
cy7c1368c | |
|
Contextual Info: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz200-mhz+1 | |
CY7C1368CContextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz | |
CY7C1368CContextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz | |
CY7C1368CContextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation ■ Optimal for performance (Double-Cycle deselect) ❐ Depth expansion without wait state ■ 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz | |
|
Contextual Info: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz200-mhz+1 | |
|
Contextual Info: CY7C1368C PRELIMINARY 9-Mb 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz200-mhz+1 | |
|
Contextual Info: THIS SPEC IS OBSOLETE Spec No:38-05686 Spec Title:CY7C1368C 9-MBIT 256 K X 32 PIPELINED DCD SYNC SRAM Sunset Owner:Jayasree Nayar (NJY) Replaced by: None CY7C1368C 9-Mbit (256 K x 32) Pipelined DCD Sync SRAM 9-Mbit (256 K × 32) Pipelined DCD Sync SRAM |
Original |
cy7c1368c32-bit250-mhz | |
|
Contextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz200-mhz+1 | |
|
Contextual Info: CY7C1368C 9-Mbit 256K x 32 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 32-bit common I/O architecture |
Original |
cy7c1368c32-bit250-mhz200-mhz+1 | |
FSQ510 Equivalent
Abstract: BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2
|
Original |
gp-20fsq510 equivalentbta12 6008bta16 6008+7 | |
CY7C1338-100AXC
Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
|
Original |
cy7c1019bv33-15vcgs71108aj-12cy7c1019bv33-15vxcgs71108agj-12+16 |