DM54L Search Results

DM54L73W

Abstract: C1995 DM54L73 DM54L73J J14A W14B
Contextual Info: DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops after a complete clock

DM54LS174

Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
Contextual Info: 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary

74LS90N

Abstract: 74LS93N om504 74ls90 function 74LS93 logic symbol 54LS90 54LS92 DM54LS90 NSB50 CI 74LS90
Contextual Info: DM54LS90/DM74LS90, DM54LS92/DM74LS92, DM54LS93/DM74LS93 Jpg National Jud Semiconductor DM54LS90/DM74LS90, DM54LS92/DM74LS92, DM54LS93/DM74LS93 Decade, Divide by 12, and Binary Counters General Description Features Each o f th e s e m o n o lith ic c o u n te rs c o n ta in s fo u r m a s te r­

DM54

Abstract: DM74
Contextual Info: DM54L54/DM74L54 National ÆjA Semiconductor DM54L54/DM74L54 4-Wide AND-OR-INVERT Gates General Description Absolute Maximum Ratings Note d This device con tains a com bination of gates w hich per­ form s the logic AND-OR-INVERT function. Supply V oltage

DM54

Abstract: DM74
Contextual Info: DM54L78/DM74L78 National SiA Semiconductor DM54L78/DM74L78 Dual Master-Slave J*K Flip-Flops with Preset, Common Clear, Common Clock, and Complementary Outputs General Description Absolute Maximum Ratings Note 1 This device con tains tw o m aster-slave J-K flip-ftops

74L164

Abstract: 54L164 DM54 DM74
Contextual Info: DM54L164A/DM74L164A National Ææ Semiconductor DM54L164A/ DM74L164A 8-Bit Serial In/Parallel Out Shift Registers General Description These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input in­

DM54

Abstract: DM74
Contextual Info: DM54L30/DM74L30 National £jm Semiconductor DM54L30/DM74L30 8-Input NAND Gate General Description Absolute Maximum Ratings Note d T h is d e vice c o n ta in s a s in g le g a te w h ic h p e rfo rm s th e lo g ic N A N D fu n c tio n . S u p p ly V o lta g e

DM74L75A

Abstract: 74l75 DM54 DM54L75A DM74
Contextual Info: DNI54L75A/DM74L75A National ÀjA Semiconductor DM54L75A/DM74L75A Quad Latches General Description Absolute Maximum Ratings Note n These latche s are ide a lly su ited fo r use a s te m p o ra ry s to r­ age fo r binary inform ation betw een p roce ssin g units and

DM54S08

Abstract: DM74L08 DM54 DM54L08 DM74 DM74S08
Contextual Info: DM54L08/DM74L08 National SiA Semiconductor DM54L08/DM74L08 Quad 2-Input AND Gates General Description Absolute Maximum Ratings Note 1 This device contains four independent gates each of w hich perform s the logic AND function. Supply Voltage Input Voltage

Contextual Info: 54LS20,DM54LS20,DM74LS20 54LS20 DM54LS20 DM74LS20 Dual 4-Input NAND Gates Literature Number: SNOS291A 54LS20 DM54LS20 DM74LS20 Dual 4-Input NAND Gates General Description Features This device contains two independent gates each of which performs the logic NAND function

Contextual Info: 54LS30,DM54LS30,DM74LS30 54LS30 DM54LS30 DM74LS30 8-Input NAND Gate Literature Number: SNOS302A 54LS30 DM54LS30 DM74LS30 8-Input NAND Gate General Description Features This device contains a single gate which performs the logic NAND function Y Alternate Military Aerospace device 54LS30 is available Contact a National Semiconductor Sales Office

74LS386N

Abstract: 54LS386 74LS386 DM54 DM74 DM74LS386 54LS386J
Contextual Info: DM54LS386/DM74LS386 National Sim Semiconductor DM54LS386/DM74LS386 Quad 2-Input Exclusive-OR Gates General Description Absolute Maximum Ratings Note 1 This device contains four independent gates each of w hich performs the logic exclusive-OR function. Supply Voltage

54LS368

Abstract: 54LS368A 54LS368ADMQB 54LS368AFMQB 54LS368ALMQB DM54LS368A DM54LS368AJ DM54LS368AW DM74LS368A DM74LS368AM
Contextual Info: 54LS368A DM54LS368A DM74LS368A Hex TRI-STATE Inverting Buffers General Description This device contains six independent gates each of which performs an inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output with

LS279

Abstract: 54LS279 54LS279DMQB 54LS279FMQB 54LS279LMQB DM54LS279 DM54LS279J DM74LS279 DM74LS279M DM74LS279N
Contextual Info: 54LS279 DM54LS279 DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs Two of the four latches have an additonal S input ANDed with the primary S input A low on any S input while the R input is high will be

54LS257A

Abstract: 54LS258A DM54LS257B DM54LS258B DM74LS257B DM74LS258B LS157 LS158
Contextual Info: 54LS257A DM54LS257B DM74LS257B 54LS258A DM54LS258B DM74LS258B TRI-STATE Quad 2-Data Selectors Multiplexers General Description Features These Schottky-clamped high-performance multiplexers feature TRI-STATE outputs that can interface directly with data lines of bus-organized systems With all but one of the

C1995

Abstract: DM54L74 DM54L74J DM54L74W J14A W14B
Contextual Info: DM54L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a

Contextual Info: May 1992 DM54LS447/DM74LS447 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs General Description The ’LS447 is the same as the ’LS247 except that the Out­ put OFF Voltage, Vqh is specified as 7.0 V rather than 15V, with the same Ioh limit of 250

dm74ls377n

Abstract: DM74LS377 DM54LS377 DM54LS377E DM54LS377J DM54LS377W DM74LS377WM E20A J20A LS377
Contextual Info: DM54LS377 DM74LS377 Octal D Flip-Flop with Common Enable and Clock General Description Features The ’LS377 is an 8-bit register built using advanced low power Schottky technology This register consists of eight D-type flip-flops with a buffered common clock and a buffered common input enable The device is packaged in the

DM74LS86

Abstract: DM54LS86J DM54LS86W DM74LS86M DM74LS86N J14A M14A N14A W14B
Contextual Info: DM74LS86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which performs the logic exclusive-OR function. Connection Diagram Dual-In-Line Package DS006380-1 Order Number DM54LS86J, DM54LS86W, DM74LS86M or DM74LS86N

Contextual Info: 54LS30 DM54LS30 DM74LS30 8-Input NAND Gate General Description Features This device contains a single gate which performs the logic NAND function Y Alternate Military Aerospace device 54LS30 is available Contact a National Semiconductor Sales Office Distributor for specifications

Contextual Info: National Semiconductor , , May 1989 54LS367A/DM54LS367A/DM74LS367A Hex TRI-STATE Buffers General Description This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

DM74LS00 function

Abstract: 54LS00DMQB DM74LS00 DM54LS00 54LS00/BCBJC
Contextual Info: June 1989 54LS00/DM54LS00/DM74LS00 Quad 2-Input NAND Gates General Description Features This device contains four independent gates each of which performs the logic NAND function. • Alternate Military/Aerospace device 54LS00 is available. Contact a National Semiconductor Sales Office/

Contextual Info: & June 1989 54LS42/DM54LS42/DM74LS42 BCD/Decimal Decoders General Description Features These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connect­ ed in pairs to make BCD input data available for decoding

Contextual Info: National Semiconductor , , May 1989 54LS368A/DM54LS368A/DM74LS368A Hex TRI-STATE Inverting Buffers General Description This device contains six independent gates each of which performs an inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit the