DIODE T12 MICROSEMI Search Results

schematic diagram UPS

Abstract: sine wave inverter circuit diagram h-bridge igbt pwm schematics circuit 500 watt inverter 12v dc to 220 ac chopper transformer FOR UPS 500 watt power circuit diagram uc3825 schematic diagram online UPS 500 va sine wave ups circuit H BRIDGE inverters circuit diagram using igbt hybrid car charger inverter schematic diagram
Contextual Info: PICREF-2 REFERENCE DESIGN Intelligent Battery Charger M PICREF-1 Uninterruptible Power Supply Reference Design INTRODUCTION PICREF-1 OVERVIEW At times, power from a wall socket is neither clean nor uninterruptible. Many abnormalities such as blackouts, brownouts, spikes, surges, and noise can occur. Under

b h21

Contextual Info: Revision 18 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

AX125

Abstract: AX2000 CQ208 CQ256 FG256 FG324 PQ208 AX2000-CQ256
Contextual Info: Revision 17 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates

ISOmodem

Abstract: schematic diagram of aoc monitor R2610 transistor S38 transistor adaa CTR21 Si2414 Si2433 Si2456 zener diode 5.6 V
Contextual Info: Si2456/Si2433/Si2414 V.90, V. 34, V. 32 B I S I S O M O D E M WITH I N T E G R A T E D G L O B A L DAA Features Data modem formats Integrated DAA ITU-T, Bell 300 bps up to 56 kbps V.42, V.42bis, MNP2-5 Automatic rate negotiation Capacitive isolation Parallel phone detect

puerto

Abstract: transistor adaa ISOmodem schematic diagram of aoc monitor "Silicon Laboratories" -si3014 si3021 560002 CTR21 Si2414 Si2433 Si2456
Contextual Info: Si2456/Si2433/Si2414 V.90, V. 34, V. 32 B I S I S O M O D E M WITH I N T E G R A T E D G L O B A L DAA Integrated DAA ITU-T, Bell 300 bps up to 56 kbps V.42, V.42bis Automatic rate negotiation Capacitive isolation S Data modem formats i2 45 6 Features

6N16

Abstract: Z51 zener diode diode b2z schematic diagram of aoc monitor mark b2Z ISOmodem CTR21 Si2414 Si2433 Si2456
Contextual Info: S i 24 56 / Si 2 43 3/ S i 24 14 V. 9 0 , V. 3 4 , V.3 2 B I S I S O M O D E M W I T H I N T E G R A T E D G L O B A L D A A Features Data modem formats Integrated DAA ITU-T, Bell 300 bps up to 56 kbps V.42, V.42bis, MNP2-5 Automatic rate negotiation Capacitive isolation

BLM18HE601SN1D

Abstract: MC853X4-035W
Contextual Info: Data Sheet May 2012 DS31404 Demo Kit General Description The DS31404DK is an easy-to-use evaluation kit for the DS31404 dual DPLL timing IC. A surface-mounted DS31404 and careful layout provide maximum signal integrity. An on-board low-phase-noise stratum 3

MC853X4-035W

Contextual Info: Data Sheet May 2012 DS31407 Demo Kit General Description The DS31407DK is an easy-to-use evaluation kit for the DS31407 timing IC. A surface-mounted DS31407 and careful layout provide maximum signal integrity. An onboard low-phase-noise TCXO is provided for device

Contextual Info: Data Sheet May 2012 DS31406 Demo Kit General Description The DS31406DK is an easy-to-use evaluation kit for the DS31406 timing IC. A surface-mounted DS31406 and careful layout provide maximum signal integrity. An onboard low-phase-noise stratum 3 quality oscillator is

Contextual Info: Data Sheet May 2012 DS31400 Demo Kit General Description The DS31400DK is an easy-to-use evaluation kit for the DS31400 dual DPLL timing IC. A surface-mounted DS31400 and careful layout provide maximum signal integrity. An on-board low-phase-noise stratum 3

Contextual Info: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

RTAX250

Abstract: RTAX4000DL RTAX4000D CG624 RTAX4000S LG1152 TRANSISTOR TB 772 SL RTAX2000S ACTEL CCGA 624 mechanical transistor prc 606 j
Contextual Info: Revision 15 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

w32 smd transistor

Abstract: rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152
Contextual Info: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)

Contextual Info: Data Sheet May 2012 DS31415 Demo Kit General Description The DS31415DK is an easy-to-use evaluation kit for the DS31415 timing IC. A surface-mounted DS31415 and careful layout provide maximum signal integrity. An onboard low-phase-noise TCXO is provided for device

Contextual Info: Data Sheet May 2012 DS3100DK Demo Kit Evaluates: DS3100 Timing IC General Description The DS3100DK is an easy-to-use demo and evaluation kit for the DS3100 Stratum 3/3E timing card IC. A surface-mounted DS3100 and careful layout provide maximum signal integrity. An on-board

LT 7202 diode

Abstract: relay btk 1012 btk 1012 lt4010 BEL 7905 c1 DIODE Z5 teltone tls 3 transformer u4f 8002 AUDIO amplifier Antenna detection u6A
Contextual Info: AN70 S i 2 4 5 6 / S i 2 4 3 3 / S i 2 4 1 4 / S i 2 4 0 3 M O D E M D E S I G N E R ’S G U I D E Introduction double-sided and single-sided layouts with options for through-hole isolation components. Additionally, evaluation boards, useful for evaluating the modem

Z51 zener diode

Abstract: Si3015-FS T1-6 Si3015FS schematic diagram of aoc monitor SI2414-FT C193 CTR21 Si2414 Si2433
Contextual Info: Si2456/33/14 V.9 0 , V.3 4 , V.3 2 B I S I SO M O D E M C H I PS E T WITH I N T E G R A T E D G L O B A L DAA Features Data modem formats Integrated DAA ITU-T, Bell 300 bps up to 56 kbps V.42, V.42bis, MNP2-5 Automatic rate negotiation Over 5000 V capacitive isolation

A2F200

Abstract: A2F200M3F A2F200M3F-FG256 A2F500 pin details A2F500 AES128 CS288 FG256 FG484 PQ208
Contextual Info: Revision 6 SmartFusion Intelligent Mixed Signal FPGAs Microcontroller Subsystem MSS • • • • • • • • • • • • Hard 100 MHz 32-Bit ARM Cortex -M3 – 1.25 DMIPS/MHz Throughput from Zero Wait State Memory – Memory Protection Unit (MPU)

Contextual Info: Revision 5 SmartFusion Intelligent Mixed Signal FPGAs Microcontroller Subsystem MSS • • • • • • • • • • • • Hard 100 MHz 32-Bit ARM Cortex -M3 – 1.25 DMIPS/MHz Throughput from Zero Wait State Memory – Memory Protection Unit (MPU)

Contextual Info: Revision 6 Fusion Family of Mixed Signal FPGAs Features and Benefits In-System Programming ISP and Security • ISP with 128-Bit AES via JTAG • FlashLock Designed to Protect FPGA Contents High-Performance Reprogrammable Flash Technology • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS

a51 ZENER DIODE

Abstract: transistor 2n2222 bipolar ROM EQUIVALENCES TRANSISTOR LIST ProASIC3 lvds yl 1060
Contextual Info: Revision 3 Fusion Family of Mixed Signal FPGAs Features and Benefits In-System Programming ISP and Security • ISP with 128-Bit AES via JTAG • FlashLock Designed to Protect FPGA Contents High-Performance Reprogrammable Flash Technology • • • •

Z51 zener diode

Abstract: ISOmodem schematic diagram of aoc monitor transistor adaa diode b2z AN48 BAV99 C193 CTR21 on-semiconductor data
Contextual Info: Si2403 V.22 B I S I S O M O D E M WITH ERROR CORRECTION Features Data modem formats Integrated DAA ITU-T, Bell 300 bps up to 2400 bps V.42, MNP2-4 Capacitive isolation Parallel phone detect Globally-compliant line interface Caller ID decode 3.3 V power

actel core 8051

Contextual Info: Revision 4 Fusion Family of Mixed Signal FPGAs Features and Benefits In-System Programming ISP and Security • ISP with 128-Bit AES via JTAG • FlashLock Designed to Protect FPGA Contents High-Performance Reprogrammable Flash Technology • • • •

Contextual Info: Revision 5 Fusion Family of Mixed Signal FPGAs Features and Benefits In-System Programming ISP and Security • ISP with 128-Bit AES via JTAG • FlashLock Designed to Protect FPGA Contents High-Performance Reprogrammable Flash Technology • • • •