M82C51A-2
Abstract: m80c88a-2 m82c51 M81C55 80C88A m80c88a M80C88A-10 m81c55-5 msm80c88a2 MSM80C85AH
Contextual Info: E2O0011-27-X2 This version: Jan. 1998 MSM80C88A-10RS/GS/JS Previous version: Aug. 1996 ¡ Semiconductor MSM80C88A-10RS/GS/JS ¡ Semiconductor 8-Bit CMOS MICROPROCESSOR GENERAL DESCRIPTION The MSM80C88A-10 is internal 16-bit CPUs with 8-bit interface implemented in Silicon Gate
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e2o0011-27-x2msm80c88a-10rs/gs/jsmsm80c88a-1016-bit+12nmos8088-1msm80c86a-10msm80c85ahm82c51a-2m80c88a-2m82c51m81c5580c88am80c88am80c88a-10m81c55-5msm80c88a2
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AU-AIS
Abstract: SDH 209 E001 IXF6012 IXF6048 55236 GCIXF6012E w213 marking tuifdp marking f25 ku
Contextual Info: Intel IXF6012 51/155/622 Mbit/s SONET/SDH Cell/Packet Interface Datasheet Intel® IXF6012 is a single-chip interface solution for the transport of ATM cells or HDLC frames over SONET/SDH. Intel® IXF6012 can operate as a quad 51/155 Mbit/s or as a single
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ixf6012au-aissdh 209e001+6ixf604855236gcixf6012ew213 markingtuifdpmarking f25 ku
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M81C55-5
Abstract: oki m82c55a-2 oki m80c85a m82c55a-2 OKI M81C55 m81c55 M82C51A-2 M82C53-2 M80C88A-2 M82C51A
Contextual Info: Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008.
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msm80c86a-10rs/gs/jsqfp56-p-1519-1m81c55-5oki m82c55a-2+8oki m80c85am82c55a-2oki m81c55m81c55m82c51a-2m82c53-2m80c88a-2m82c51a
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AVR220
Abstract: CNT1 BUBBle Sort
Contextual Info: AVR220: Bubble Sort Features • 14-Word Subroutine Sorts up to 255 Bytes of Data • Runable Demo Program Introduction This application note implements the Bubble Sort algorithm on the AVR controllers. The subroutine “bubble” sorts up to 224 bytes of SRAM data which is the
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SAB 8155 p
Abstract: SAB 8085 A-P how to interface 8085 with 8155 SAB 8088-1-P SAB 8155 8287a design adc interfaces with 8088 microprocessor pin diagram of ic 8088 8283a sab8085
Contextual Info: SAB 8088 8-Bit Microprocessor Preliminary SAB 8088 5 MHz SAB 8088-2 8 MHz SAB 8088-1 10 MHz • 8-bit data bus interface • 16-bit internal architecture • Direct addressing capability to 1 Mbyte of memory • Software compatible with SAB 8086 • 14-word by 16-bit register set with
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sab808816-bit14-word40-pin+13p-dip-40pl-cc-44a19/se-a16/s3sab 8155 psab 8085 a-phow to interface 8085 with 8155sab 8088-1-psab 81558287adesign adc interfaces with 8088 microprocessorpin diagram of ic 80888283asab8085
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27mhz remote control transmitter circuit
Abstract: 27mhz remote control transmitter schematics 506K LLC resonant full bridge schematic LEONE RELAY sc5 27mhz remote car Taiwan Semiconductor 6A BEL 7905 c1 TRANSISTOR FS 2025 diode Marking codes u1d ON
Contextual Info: AN93 S i 2 4 9 3 / S i 2 4 5 7 / S i 2 4 3 4 / S i 2 4 1 5 / S i 2 4 0 4 M o d e m D e s i g n e r ’s G u i d e Introduction double-sided and single-sided layouts with options for through-hole isolation components. Additionally, evaluation boards, useful for evaluating the modem
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si2493/si2457/si2434/si2415si240427mhz remote control transmitter circuit27mhz remote control transmitter schematics+8506kllc resonant full bridge schematicleone relay sc527mhz remote cartaiwan semiconductor 6abel 7905 c1transistor fs 2025diode marking codes u1d on
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54F10
Abstract: 74F10 E28A
Contextual Info: April 1989 9403A First-In First-Out FIFO Buffer Memory General Description Features The 9403A is an expandable fa ll-through type high-speed First-In First-O ut (FIFO) B utter M em ory optim ized fo r high speed disk or tape co ntrollers and com m unication buffer
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9403A-C
Contextual Info: April 1989 Semiconductor & 9403A First-In First-Out FIFO Buffer Memory General Description Features The 9403A is an expandable fall-through type high-speed First-In First-Out (FIFO) Buffer Memory optimized for high speed disk or tape controllers and communication buffer
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P80A49H
Abstract: 8035HL F1L 250 V fuse BPK-70 interfacing 8275 crt controller with 8086 i8282 hall marking code A04 Transistor AF 138 DK55 82720 intel
Contextual Info: COMPONENT DATA CATALOG JANUARY 1982 Intel C orporation makes no w arranty fo r the use of its products and assumes no re sponsib ility fo r any e rrors w hich may appear in th is docum ent nor does it make a com m itm ent to update the info rm atio n contained herein.
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rmx/80p80a49h8035hlf1l 250 v fuse+7bpk-70interfacing 8275 crt controller with 8086i8282hall marking code a04transistor af 138dk5582720 intel
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BT8233EHFB
Abstract: 5969b l8233
Contextual Info: R O C K W E L L Network access S E M I C O N D U C T O R Bt8233 ATM ServiceSAR with S Y S T E M S xBR Traffic Management datasheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Bt8233 ATM ServiceSAR with xBR Traffic Management The Bt8233 Service Segmentation and Reassembly Controller integrates in a single
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Equivalent IRF 44
Abstract: fifo buffer m 9403 1N3064 9403
Contextual Info: Signetics 9403 64-Bit FIFO Buffer Memory Product Specification Logic Products FEATURES FUNCTIONAL DESCRIPTION • 10MHz Serial or Parallel Data Rate • Serial or Parallel Input and Output • Expandable Without External Logic • Three-State Outputs • Fully TTL-Compatlble
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64-bit10mhz24-pinequivalent irf 44+4fifo bufferm 94031n30649403
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IRF 950
Abstract: 74F403A 74F403ASPC N24C
Contextual Info: Revised May 1999 74F403A First-In First-Out FIFO Buffer Memory General Description Features The 74F403A is an expandable fall-through type highspeed First-In First-Out (FIFO) Buffer Memory optimized for high-speed disk or tape controllers and communication
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74F403A
Abstract: 74F403ASPC MS-001 N24C
Contextual Info: Revised October 2000 74F403A First-In First-Out FIFO Buffer Memory General Description Features The 74F403A is an expandable fall-through type highspeed First-In First-Out (FIFO) Buffer Memory optimized for high-speed disk or tape controllers and communication
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I960CA
Abstract: CRC10 RS8234 RS8250 on-demand multicast messages
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and
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F433
Contextual Info: 433 54F/74F433 First-In First-Out FIFO Buffer Memory Connection Diagrams Donription J n y P u t o f i an expandable fall-through type high-speed first-in first-o u t * I F O )Jm ijm J*WLory tha t is op tim ize d fo r high-speed d isk o r tape c o n trc M e y iy K m a fc u n ic a tio n b u ffe r ap plicatio ns. It is organized as 64
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AU-AIS
Abstract: W120 AH20 AK21 IXF6048 R256000
Contextual Info: IXF6048 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface Datasheet IXF6048 is a single-chip interface solution for the transport of ATM cells or HDLC frames over SONET/SDH. IXF6048 can operate as a quad 51/155/622 Mbit/s or as a single 2488 Mbit/s SONET/SDH processor. When configured in ATM UNI mode, it interfaces with an ATM layer
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delta dps 298 cp
Abstract: delta dps 298 cp-1 IRF 8030 irf 4710 bbc 598 479 DIODE F4049 sn 94042 Switching power supplies Delta electronics dps MR 4710 ci 4047B
Contextual Info: FAIRCHILD BIPOLAR M IC R O P R O C E S S O R □ATABOOK MACROLOGIC BIPOLAR MICROPROCESSOR OATABOOK FAIRCHILD 4 6 4 Ellis S tre e t, M o u n ta in V ie w , C alifo rn ia 9 4 0 4 2 c 1976 F a i r c h il d C a m e r a a n d In s t r u m e n t C o r p o r a t i o n / 4 6 4 E llis S t r e e t , M o u n t a i n V i e w , C a li f o r n ia 9 4 0 4 2 / 4 1 5 9 6 2 - 5 0 1 1 / T W X
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corporation/464962-5011/twxtech-71-038delta dps 298 cp+9delta dps 298 cp-1irf 8030irf 4710bbc 598 479 diodef4049sn 94042switching power supplies delta electronics dpsmr 4710ci 4047b
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IRF48
Abstract: XC115 a31X ScansUX1004
Contextual Info: 9403 FIRST-IN FIRST-OUT FIFO BUFFER MEMORY FA IR CH ILD TTL MACROLOGIC DESCRIPTION - The 9403 is an expandable fall-through type high-speed First-In First-Out (FIFO) Buffer Memory optimized for high speed disc or tape controllers and communication buffer applications. It is organized as 16 words by four bits and may be
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AVR220: Bubble Sort
Abstract: AVR220 Sort 14-WORD CNT1
Contextual Info: AVR220: Bubble Sort Features • 14-word Subroutine Sorts up to 255 Bytes of Data • Runable Demo Program Introduction This application note implements the Bubble Sort algorithm on the AVR controllers. The subroutine “bubble” sorts up to 224 bytes of SRAM data which is the SRAM area
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s 15018
Contextual Info: N T E ELECTRONIC?; TNC_ ¿ s e ]> • b 4 3 1 5 S ci 0 0 0 5 7 0 3 2bb H N T E T -S # 'O l POSITIVE, 3 TERMINAL, ARRANGED BY OUTPUT VOLTAGE Vottag* n Regulated Voltage Out ±5% Volti) KTEfype Number Cm * Styl« (Vo«*) Diagram Number V«ui V* Hu urn
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403F
Contextual Info: 03 National ÆM Semiconductor 54F/74F403A First-In First-Out FIFO Buffer Memory General Description Features The ’F403A is an expandable fall-through type high-speed First-In First-Out (FIFO) Buffer Memory optimized for high speed disk or tape controllers and communication buffer
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t04 68 3 pin transistor
Abstract: MD 202 flame relay AC03 nec alps lcd 14 pin t04 68 3 pin diode transistor z5t S3043 S3044 STM-16 z046
Contextual Info: User’s Manual µPD98414 NEASCOT-P70TM ATM 2.4Gbps SONET Framer Document No. S14166EJ4V0UM00 (4th edition) Date Published December 2001 J CP(K) 1999 1991 Printed in Japan [MEMO] 2 User's Manual S14166EJ4V0UM SUMMARY OF CONTENTS CHAPTER 1 GENERAL .13
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iC-lg
Abstract: MSM80C86A-10RS -7 80C85AH
Contextual Info: O K I Semiconductor MSM80C86A-1ORS/GS/JS 16-Bit C M O S M ICROPROCESSOR G E N E R A L D ESCR IPTIO N The MSM80C86A-10is com plete 16-bit CPUs im plem ented in Silicon Gate CMOS technology. They are designed w ith sam e processing speed as the NM OS 8086-1 b u t have considerably less pow er
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CN8234
Abstract: BT82
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and
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