D35B 80 Search Results

D35B

Abstract: D35B 60 pqfp132 TEF 2421 TQFP 144 PACKAGE D26B D35A
Contextual Info: 512 & 1024 x 36 × 2 BiFIFOs LH543611/21 TIMING DIAGRAMS t RS RS t RSS t RSH t RSS CKA t ES t EH t ES t EH tRQS tRQH tRQS tRQH EN A REQA t RSS t RSH t RSS CK B t ES t EH t ES t EH tRQS tRQH tRQS tRQH EN B REQB t RF EF, AE t RF HF, AF, FF, MBF NOTES: 1. RS overrides all other input signals, except for R/WA, ENA, and REQA. It operates

D35B

Abstract: D35B 60 D11A D12A D15A D18A LH5420 LH543601 D-33A
Contextual Info: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite

D35B

Abstract: D10A D11A D12A D15A LH5420 LH543601 D23B
Contextual Info: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite

D35B 60

Abstract: D35B diode A1A 115 16 QS3383 D35A QS32383 D17A-D9A D0B-D35B D35B 60 74
Contextual Info: QS723611, QS723621 PRELIMINARY High-Speed CMOS High Speed CMOS 512Bus x 36Exchange x 2/1K x 36 x 2 Switches FIFO Bi-directional Q QS3383 QS723611 QS32383 QS723621 FEATURES/BENEFITS DESCRIPTION • Fast cycle times: 20/25/30/35 ns 50/40/33/28 MHz • Functionally Upwards-Compatible with

D35B 60

Abstract: D35B D35B 60 74 D35B 80 D35B 60 89 D11A D12A LH5420 LH543601 LH543611
Contextual Info: LH543611/21 512 x 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Pin-Compatible and Functionally The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.

d358

Abstract: D35B pitch 0.4 QFP 256p D20B D22B D24B D268 D28B LH5420 LH543620
Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 x 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width FUNCTIONAL DESCRIPTION

D22A

Contextual Info: LH5420/ 256 FEATURES X 36 X 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION • Fast Cycle Times: 25/30/35 ns • Two 256 x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width on Port B • Fully Asynchronous Port-to-Port Communications

L2735

Abstract: D-34A i-box
Contextual Info: LH543611/21 512x36x2/1024x36x2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • The LH543611 and LH543621 contain two FIFO buff­ ers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.

aei cr

Abstract: a04l
Contextual Info: ADVANCE INFORMATION LH54V3611/21 FEATURES • Upwards-Compatible with Sharp LH543611/21 • Cycle Time as fast as 15 ns • Two 512 x 36-bit FIFO Buffers LH54V3611 or Two 1024 x 36-bit FIFO Buffers (LH54V3621) • Selectable 36/18/9-bit Word Width on Port B;

u29a

Abstract: bd248 MS76542-SSFC
Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 25/30/35 ns The LH5420 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite direc­ tions, for bidirectional data buffering. FIFO #1 and FIFO

D2SB 73

Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 • PQFP to PGA Package Conversion * x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width

D2SB 73

Contextual Info: 256 x 36 x 2 /512 x 36 x 2 BiFIFOs FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 15/20/25/30/35 ns The LH543601/11 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and

KM48V2100B

Abstract: 2100BK
Contextual Info: KM48V2100BK CMOS DRAM ELECTRONICS 2 M x 8 B i t CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , refresh

d19b

Contextual Info: QS723611, QS723621 PRELIMINARY Q High-Speed CMOS 5 1 2 X 3 6 X 2 /1 K X 3 6 X 2 Bi-directional FIFO QS723611 QS723621 FEATURES/BENEFITS DESCRIPTION • Fast cycle times: 20/25/30 ns 50/40/33 MHz • Functionally Upwards-Compatible with QS725420A • Two 512 x 36-bit (QS723611) or 1K x 36-bit

2sa 1023

Contextual Info: QS723611, QS723621 PRELIMINARY Q High-Speed CMOS 5 1 2 X 3 6 X 2 /1 K X 3 6 X 2 Bi-directional FIFO DESCRIPTION FEATURES/BENEFITS Fast cycle times: 20/25/30/35 ns 50/40/33/28 MHz Functionally Upwards-Compatible with QS725420A Two 512 x 36-bit (QS723611) or 1K x 36-bit

tda ic

Contextual Info: QS725420A PRELIMINARY High-Speed CMOS 256 x 36 x 2 Bi-directional FIFO ô QS725420A FEATURES/BENEFITS • Fast cycle tim es: 20/25/30/35 ns • T w o 256 x 36-bit FIFO buffers • Full 36-bit word width • Selectable 36/18/9-bit word width on port B • Fully asynchronous operation of port A and port B

DL2AD

Contextual Info: LH543601 256 x 36 x 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns The LH543601 contains two FIFO1buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and

Contextual Info: L H 5 4 3 6 1 1 / 2 1 512x36x2/1024x36x2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • The LH543611 and LH543621 contain two FIFO buff­ ers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.

Contextual Info: COVER DATA SHEET 32GB DDR3L SDRAM Load Reduced DIMM EBJ34LH4E6PA 4096M words 72 bits, 4 Ranks Specifications Features • Density: 32GB • Organization — 4096M words  72 bits, 4 ranks • Mounting 36 pieces of 8G bits DDR3L SDRAM with DDP (FBGA)

Contextual Info: COVER DATA SHEET 32GB DDR3 SDRAM Load Reduced DIMM EBJ34LH4B6PA 4096M words 72 bits, 4 Ranks Specifications Features • Density: 32GB • Organization — 4096M words  72 bits, 4 ranks • Mounting 36 pieces of 8G bits DDR3 SDRAM with DDP (FBGA)

U24A

Contextual Info: LH543601/11 PRODUCT PREVIEW 256 x 36 x 2 / 512 x 36 x 2 BiFIFOs FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 15/20/25/30/35 ns The LH543601/11 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and

d22a

Contextual Info: QS725420A High-Speed CMOS 256 x 36 x 2 Bi-directional FIFO Q QS725420A FEATURES/BENEFITS • • • • • • • Fast cycle times: 20/25/30 ns Two 256 x 36-bit FIFO buffers Full 36-bit word width Selectable 36/18/9-bit word width on port B Fully asynchronous operation of port A and port B

Contextual Info: LH5420 FUNCTIONAL DESCRIPTION FEATURES • Fast Cycle Times: 25/30/35 ns • Two 256 • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width on Port B • Independently-Synchronized ‘Fully Asynchronous' Operation of Port A and Port B • ‘Synchronous’ Enable-Plus-Clock Control

Contextual Info: MPLAB Starter Kit for Intelligent.Integrated.Analog User’s Guide  2013 Microchip Technology Inc. DS50002172A Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet.