D35A Search Results

72V3680

Contextual Info: 3.3 VOLT HIG H-DENSITY SUPERSYNC II 36-B IT FIFO 4,096 x 36 8,192 x 36 1 6 ,3 8 4 x 3 6 32,768 x 36 65,536 x 36 131,072 x 36 P R E L IM IN A R Y ID T 72V 3660 ID T 72V 3670 ID T 72V 3680 ID T 72V 3690 ID T 72V 36100 ID T 72V 36110 FEATURES: Auto power down minimizes standby power consumption

kb3886

Abstract: NPN transistor c828 smd diode S6 58a 218S4EASA32HK SB400 LM13W SOT-26 F14 w27 smd transistor diode C940 ST ak7 SMD Transistor KB3886 B1
Contextual Info: 5 3 2 1 First International Computer,Inc Portable Computer Group HW Department D C 4 Board name : Mother Board Schematic 1. Schematic Page Description : Project : LM13 2. PCI & IRQ & DMA Description : Version : 0.3 3. Block Diagram : D C 4. Net name Description :

diode in40

Abstract: Diode Mark ON B14 Q127 xn13
Contextual Info: 1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 40 BIT WIDE CONFIGURATION IDT72P51767 IDT72P51777 5,242,880 bits 10,485,760 bits FEATURES • • • • • • • • • • • • Choose from among the following memory density options: IDT72P51767  Total Available Memory = 5,242,880 bits

d358

Abstract: D35B pitch 0.4 QFP 256p D20B D22B D24B D268 D28B LH5420 LH543620
Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 x 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width FUNCTIONAL DESCRIPTION

D35B 60

Abstract: D35B D35B 60 74 D35B 80 D35B 60 89 D11A D12A LH5420 LH543601 LH543611
Contextual Info: LH543611/21 512 x 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Pin-Compatible and Functionally The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.

D2SB 73

Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 • PQFP to PGA Package Conversion * x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width

D35B

Abstract: D35B 60 pqfp132 TEF 2421 TQFP 144 PACKAGE D26B D35A
Contextual Info: 512 & 1024 x 36 × 2 BiFIFOs LH543611/21 TIMING DIAGRAMS t RS RS t RSS t RSH t RSS CKA t ES t EH t ES t EH tRQS tRQH tRQS tRQH EN A REQA t RSS t RSH t RSS CK B t ES t EH t ES t EH tRQS tRQH tRQS tRQH EN B REQB t RF EF, AE t RF HF, AF, FF, MBF NOTES: 1. RS overrides all other input signals, except for R/WA, ENA, and REQA. It operates

D35B

Abstract: D35B 60 D11A D12A D15A D18A LH5420 LH543601 D-33A
Contextual Info: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite

D35B

Abstract: D10A D11A D12A D15A LH5420 LH543601 D23B
Contextual Info: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite

Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 E1234567489A4BCDCEEFEFEEEEEE E EEEEEEEE E E 8E 123314567891A758BCD814E1F3D167D1F1C5A36 3E1E E!77" #$%&' E!77*E+,-./E,FE1E%&EF

Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 81234536117889ABACDEFA8D98888 8 88888888 8 88888888 8 8 A81C 123314567891A758BCD814E1F3D167D1F1C5A36 ABD88EC8 7DE !"#$882%&1' 8%98CC8 !8AABA9

63D34

Contextual Info: 123456789AB89C5DEF6 695CA895C 19C8789A  8985CA   4!"4D1# 17 1234546789A8BC728DEF 25472888A8DEF  F3 !"# 1"!$FB5$%F3B9D7&936B62 1

bd1ad

Contextual Info: 1 111111111111111 1111111 1 111111111111111 1 111111111111111 1 111111111111111 1 1 123456371511234189A1BCDEF1 1 1AAA1 1 11111 1 11111111 1 1 1 12341FF13E1CFC 1111111 1 1111111 1 11111111 1 11111111 1 11111111 1 1 21F 123314567891A758BCD814E1F3D167D1F1C5A36

Contextual Info: 1 111111111111111 11111 1 111111111111111 1 111111111111111 1 111111111111111 1 1 123456789AB11CDEDFD1C111 111111111 1 11111111 1 11 D14F 123314567891A758BCD814E1F3D167D1F1C5A36 DE11D16A99  !"#$%&16A991' 4*+1(C1,FF1!"#1DDEDC

57E6

Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 81234567889ABACDEFA8D98888888 8 88888888 8 88888888 8 88888888 8 8 A87C 123314567891A758BCD814E1F3D167D1F1C5A36 3AB88DA8 DE !"#$%88&'7 8&981CC8!"#8AABA9

Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 81234567889ABACDEFA8D98888 8 88888888 8 88888888 8 88888888 8 8 A8C 123314567891A758BCD814E1F3D167D1F1C5A36 3ABD818DBAFA86 DE !"#$86%8&'  *8'981CC8 !8AABA9

Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 1234567895AABCDCEFCAFB CAE 1 23314567891A758BCD814E1F3D167D1F1C5A36 CDFAAEA585 F !"#$%A588A&' 3 *A'BAEEA!"ACCDCB 1234565 (+2&,-2(&+.

A42 BF 331

Contextual Info: 12345634789A6BC 1DE48F75ECF34E87C2345C7D5E C9AA2 E 3F374C2!CC9"C#$%& 'EF34EC C12B96C2!C#$%#  F3 !" FB5#1333B9D7$936B62 'B 2AB9 3 !" 3

Contextual Info: 1 1111111111111 111111 1 1111111111111 1 1111111111111 1 1111111111111 1 1 8123456667889ABACDEFA8D98888888 8 88888888 8 88888888 8 88888888 8 8 A8C 123314567891A758BCD814E1F3D167D1F1C5A36 ABD888A86 3DE !"#$%8668&1' 8198*CC8!"8AABA9

81C61

Contextual Info: 1 111111111111111 11111 1 111111111111111 1 111111111111111 1 111111111111111 1 1 1234536787119ABACDEFA1D91111111 1 11111111 1 11111111 1 11 A1C 123314567891A758BCD814E1F3D167D1F1C5A36 AB1DA167 4DE !"#$%168812&' 1291CC1!"#1AABA9

tda ic

Contextual Info: QS725420A PRELIMINARY High-Speed CMOS 256 x 36 x 2 Bi-directional FIFO ô QS725420A FEATURES/BENEFITS • Fast cycle tim es: 20/25/30/35 ns • T w o 256 x 36-bit FIFO buffers • Full 36-bit word width • Selectable 36/18/9-bit word width on port B • Fully asynchronous operation of port A and port B

Contextual Info: AN-29: PARITY CHECKING IN THE QS725420A BI-FIFO Q Parity Checking in the QS725420A INTRODUCTION The QS725420A 36-bit wordwidth makes it the ideal choice for those 32-bit or 64-bit systems which use parity. WHAT IS PARITY? Many systems need to have error detection and

pwm oscillator ic 3524

Contextual Info: TLC5970 www.ti.com SBVS140A – MARCH 2010 – REVISED MAY 2010 3-Channel, 12-Bit, PWM LED Driver with Buck DC/DC Converter and Differential Signal Interface Check for Samples: TLC5970 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • •

L2735

Abstract: D-34A i-box
Contextual Info: LH543611/21 512x36x2/1024x36x2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • The LH543611 and LH543621 contain two FIFO buff­ ers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.