LH5420 Search Results

d358

Abstract: D35B pitch 0.4 QFP 256p D20B D22B D24B D268 D28B LH5420 LH543620
Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 x 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width FUNCTIONAL DESCRIPTION

D2SB 73

Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 • PQFP to PGA Package Conversion * x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width

D22A

Contextual Info: LH5420/ 256 FEATURES X 36 X 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION • Fast Cycle Times: 25/30/35 ns • Two 256 x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width on Port B • Fully Asynchronous Port-to-Port Communications

vhdl code for fifo

Abstract: free vhdl code sample vhdl code for memory write
Contextual Info: VHDL Behavioral FIFO Models VHDL BEHAVIORAL FIFO MODELS DEVICES SUPPORTED MODEL INCLUDES PART NUMBER ORGANIZATION • Source Code LH5420 256 x 36 x 2 • Test Bench LH543620 1K x 36 • User's Documentation LH540215 5 12 x 18 • Free Technical Support LH540225

organizational structure samsung

Abstract: CYPRESS SAMSUNG CROSS REFERENCE DALLAS cross reference VITELIC MK4501 ic cross reference book CY7C408 mosel KM75C02
Contextual Info: FIFO Cross Reference FIFO CROSS REFERENCE ORGANIZATIONAL STRUCTURE SHARP MODEL * COMPETITIVE VENDOR 256 X 36 X 2 LH5420 LH5481 64 X 8 64 X 9 LH5491 4,096 X 9 4,096 X 9 4,096 X 9 1,024 X 9 2,048 X 9 X LH5493 LH5494 LH5496/96H 512 X 9 4.096 LH5492 9 LH5497/97H

Contextual Info: LH5420 FUNCTIONAL DESCRIPTION FEATURES • Fast Cycle Times: 25/30/35 ns • Two 256 • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width on Port B • Independently-Synchronized ‘Fully Asynchronous' Operation of Port A and Port B • ‘Synchronous’ Enable-Plus-Clock Control

lj26

Abstract: D35B D35A
Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 x 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width FUNCTIONAL DESCRIPTION

DNA 1001 DL

Abstract: DSB45 D-33A D35B 60 74
Contextual Info: LH543611/21 512x36x2/1024x36 x2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Pin-Compatible and Functionally Upwards-Compatible with Sharp LH5420 and LH543601, but Deeper • Expanded Control Register that is Fully Readable as well as Writable

Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION FEATURES • Fast Cycle Times: 25/30/35 ns • Two 256 • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width on Port B • Fully Asynchronous Port-to-Port Communications • ‘Synchronous’ Enable-Plus-Clock Control

u29a

Abstract: bd248 MS76542-SSFC
Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 25/30/35 ns The LH5420 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite direc­ tions, for bidirectional data buffering. FIFO #1 and FIFO

D35B 60

Abstract: D35B D35B 60 74 D35B 80 D35B 60 89 D11A D12A LH5420 LH543601 LH543611
Contextual Info: LH543611/21 512 x 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Pin-Compatible and Functionally The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

D35B

Abstract: D35B 60 D11A D12A D15A D18A LH5420 LH543601 D-33A
Contextual Info: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite

D35B

Abstract: D10A D11A D12A D15A LH5420 LH543601 D23B
Contextual Info: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite

Contextual Info: LH543620 FEATURES • Fast Cycle Times: 20/25/30 ns • Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port • ‘Synchronous’ Enable-Plus-Clock Control at Both Ports • Independently-Synchronized Operation of Input Port and Output Port

d22a

Contextual Info: QS725420A High-Speed CMOS 256 x 36 x 2 Bi-directional FIFO Q QS725420A FEATURES/BENEFITS • • • • • • • Fast cycle times: 20/25/30 ns Two 256 x 36-bit FIFO buffers Full 36-bit word width Selectable 36/18/9-bit word width on port B Fully asynchronous operation of port A and port B

D2SB 73

Contextual Info: 256 x 36 x 2 /512 x 36 x 2 BiFIFOs FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 15/20/25/30/35 ns The LH543601/11 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and

Contextual Info: ADVANCE INFORMATION LH543611/21 5 1 2 x 3 6 x 2 /1 0 2 4 x 3 6 x 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns The LH543611/21 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite

Contextual Info: LH543620 FEATURES • Fast Cycle Times: 20/25/30 ns • Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port • ‘Synchronous’ Enable-Plus-Clock Control at Both Ports • Independently-Synchronized Operation of Input Port and Output Port

AP9A416

Abstract: 25bcompatible
Contextual Info: ptos AP9A415/16 Bold Italic = Enhanced Mode 512 x 18/1024 x 18 Synchronous CMOS FIFO Features • May be cascaded for increased depth or paralleled for • Fast access times: 20,25,35 ns increased width • Pin-compatible, drop-in replacements for • 16 mA I ql three-state outputs

Contextual Info: MEMORIES ★Under development • FIFO M emories Capacity Conlfeuralion word* x bits 64x8 0.5k 64 x 9 4.5k 512x9 1k x 9 9k 512 x 18 2k x 9 18k 1k x 18 256 x 36 x 2 4k x 9 36k 1k x 36 72k QFJ=PLCC 8k x 9 Modal No. LH5481D/U-25 LH5481D/U-35 LH5491D/U-25 LH5491D/U-35

Contextual Info: LH543601 256 x 36 x 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and

hitachi ic 29050 h

Abstract: 0/hitachi ic 29050 h semiconductor cross reference
Contextual Info: SEMI-CONDUCTOR Cross Reference AMD Device P/N RNP/N Fujitsu P/N RNP/N Intel P/N A M 29030 P G A -1 46C H 3-S B500 PG A -064A H 3-S P 54C A M 29117 P G A -0 68C H 3-S B2000 P G A -135A H 3-S i860 i486 A M 29325 PG A-145AH 3-5 C440H PG A -064A H 3-S AM 29331

HD68HCOOOY12

Abstract: HD64400 ad 7137 CY7C9101 8207 siemens MOTOROLA 68012
Contextual Info: SOCKETS S E M I-C O N D U C T O R CRO SS REFERENCE AMD Device P/N AM29030 AM29117 AM29325 AM29331 AM 29334 3500 SERIES AM80186 AM80286 A9850 AM95C60 AM 29000 AM29050 RN P/N PGA-146CH3-S PGA-068CH3-S PGA-145AH3-5 PGA-120BH3-S PGA-120BH3-S PGA-169BH3-S PGA-068CH3-S