LH543620 Search Results

intel 80286

Abstract: EN01 LH543620 LH543620P-20 78xxX
Contextual Info: LH543620 1024 x 36 Synchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30 ns The LH543620 is a FIFO First-In, First-Out memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can

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Contextual Info: LH543620 ADVANCE INFORMATION 1024 x 36 Synchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30 ns The LH543620 is a FIFO First-In, First-Out memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can

vhdl code for fifo

Abstract: free vhdl code sample vhdl code for memory write
Contextual Info: VHDL Behavioral FIFO Models VHDL BEHAVIORAL FIFO MODELS DEVICES SUPPORTED MODEL INCLUDES PART NUMBER ORGANIZATION • Source Code LH5420 256 x 36 x 2 • Test Bench LH543620 1K x 36 • User's Documentation LH540215 5 12 x 18 • Free Technical Support LH540225

Contextual Info: LH543620 FEATURES • Fast Cycle Times: 20/25/30 ns • Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port • ‘Synchronous’ Enable-Plus-Clock Control at Both Ports • Independently-Synchronized Operation of Input Port and Output Port

Contextual Info: SHARP LH543620 Data Sheet 1024 x 36 Synchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30 ns The LH543620 is a FIFO First-In, First-Out memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can

Contextual Info: LH543620 FEATURES • Fast Cycle Times: 20/25/30 ns • Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port • ‘Synchronous’ Enable-Plus-Clock Control at Both Ports • Independently-Synchronized Operation of Input Port and Output Port

Contextual Info: LH543620 1024 x 36 Synchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30 ns The LH543620 is a FIFO First-In, First-Out memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can

Contextual Info: LH543620 FEATURES • Fast Cycle Times: 15/20/25/30 ns • Selectable 36/18/9-Bit Word Width on Both Input Port and Output Port • ‘Synchronous’ Enable-Plus-Clock Control at Both Ports • Independently-Synchronized Operation of Input Port and Output Port

synchronous fifo

Abstract: EN01 LH543620 LH543620P-20
Contextual Info: LH543620 1024 x 36 Synchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30 ns The LH543620 is a FIFO First-In, First-Out memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can

Contextual Info: 1024 x 36 Synchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30 ns The LH543620 is a FIFO First-In, First-Out memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can replace four or more nine-bit-wide FIFOs in many appli­

intel 80286

Abstract: MEF .063 marking N5 RF EN01 LH543620 LH543620P-20 TEF 2421 2421 synchronous circuit TEF 2423 MARKING Q33
Contextual Info: LH543620 1024 x 36 Synchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30 ns The LH543620 is a FIFO First-In, First-Out memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can

n 18k U

Abstract: 132-QFP
Contextual Info: MEMORIES FIFO Memories T ype C a p a c ity Shallow Asynch. B it c o n fig u ra tio n Model No. O p e ra tin g fre q u e n c y MHz 25 64x8 LH5481 64x9 LH5491 35 0.5k A c c e s s tim e (n s ) 15 D eeper Asynch 20 25 35 50 LH5496 4.5k 512x9 9k 1k x 9 LH540202

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

D2SB 73

Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 • PQFP to PGA Package Conversion * x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width

QS72215

Abstract: DESIGN AND IMPLEMENTATION OF SYNCHRONOUS FIFO QS32383 QS3383
Contextual Info: QS72215, QS72225 High-Speed CMOS High Speed CMOS 512Bus x 18,Exchange 1K x 18 Parallel Clocked SwitchesFIFO Q QS3383 QS72215 QS32383 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 1024 x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating

Contextual Info: QS72215, QS72225 Q High-Speed CMOS 512 X 1 8 ,1K X 18 Parallel Synchronous FIFO QS72215 QS72225 FEATURES • Fast Cycle Times 20/25/35 ns • Pin-Compatible Drop-In Replacements for IDT72215LB/25LB FIFO's • Choice of Standard or Enhanced Operating Mode • Device Comes Up into One of Two Known Default

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3C08N ir2c53 ir2c05 li3301 IR3Y08 IR2E02
Contextual Info: Index Model No. IR3T ARM710 ARM7DI ARM7DM ARM7TDMI ARM7TDMI-SPL ARM8 ARM810 CMOS CMOS CMOS CMOS F series G series J series K series ID22 series ID222XX ID223XX ID224XX ID226XX ID227XX ID229XX ID22DXX ID22FXX ID22HXX ID240 series ID240DXX ID240EXX ID240GXX

Contextual Info: 2048 x 18 / 4096 x 18 S ynchrono us FIFOs FEATURES • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • 16 mA-IOL High-Drive Three-State Outputs • Pin-Compatible Drop-In Replacements for IDT72235B/45B FIFOs

LH540235

Abstract: LH540245 LH543620
Contextual Info: LH540235/45 2048 x 18 / 4096 × 18 Synchronous FIFOs • May be Cascaded for Increased Depth, or FEATURES Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for • 16 mA-IOL High-Drive Three-State Outputs

PEm 0549

Contextual Info: SH A R P Data Sheet LH540235/45 2048 x 18 / 4096 x 18 Synchronous FIFOs FEATURES • Fast Cycle Times: 20/25/35 ns • Pin-Compatible Drop-In Replacements for IDT72235B/45B FIFOs • May be Cascaded for Increased Depth, or Paralleled for Increased Width •

RJH 32

Contextual Info: 512 x 18/1024 x 18 Synchronous FIFO FEATURES • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • 16-mA-l<x Three-State Outputs • Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs • Choice of IDT-Compatible or Enhanced Operating

lj26

Abstract: D35B D35A
Contextual Info: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 x 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width FUNCTIONAL DESCRIPTION

Contextual Info: LH540215/25 FEATURES 512 x 18 /1 0 2 4 x 18 Synchronous FIFO • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty; ‘Almost’ Flags are