144TQFP Search Results

64-TQFP

Abstract: 144TQFP 44PQFP 144-TQFP
Contextual Info:  TSI Family Products Cross Reference Guide IDT Part Number Available Packages Designation Mitel Cross (* Pin Compatible) Mitel Packages (Designation) IDT72V71660 208PQFP (DR), 208BGA (BF) IDT72V73260 144TQFP (DA), 144BGA (BB) IDT72V71650 144TQFP (DA), 144BGA (BB)

QL3004

Abstract: PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040
Contextual Info: QuickSheet#4 pASIC FPGA Families High-Speed, Low Power, Instant-On, High Security FPGAs pASIC Family Highlights • High performance over 400 MHz • 100% routability and pin stability • Instant-On capability • High security and reliability • Low power

EPC1213PC8

Abstract: EPC1PC8 EPC2LC20 epc2tc32 EPC4QC100 EPM7128* kit NIOS-EVALKIT-1C12 EPC1441PC8 EPC16UC88 EPM1270F256C5ES
Contextual Info: NEW! Package 100-TQFP 100-TQFP 100-TQFP 44-TQFP 44-TQFP 44-TQFP 44-TQFP 84-PLCC 100-TQFP 100-TQFP 100-TQFP 144-TQFP 100-TQFP 100-TQFP 144-TQFP * Tube CPLD’s Cont. Macro Cells Logic Elements Pin-Pin Delay (ns) I/O Pins Voltage Speed (NS) 64 64 64 64 64

PM7202

Abstract: bel 188 transistor pnp ST7032 10BASE2 10BASE5 P996 AMD PROMS SA5-27
Contextual Info: Am79C961A PCnet -ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Industry Standard Architecture ISA and Extended Industry Standard Architecture (EISA) buses

Contextual Info: Intel386 EX EMBEDDED MICROPROCESSOR 1.0 INTRODUCTION The Intel386™ EXTB embedded processor operates at 20 or 25 MHz at 3 Volts nominal. The Intel386 EXTC embedded processor operates at 25 or 33 MHz at 5 Volts. In this datasheet, “Intel386 EX processor” refers to

Contextual Info: xr XR17C158 5V PCI BUS OCTAL UART JANUARY 2005 REV. 1.4.2 GENERAL DESCRIPTION The XR17C1581 158 is an octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication

Contextual Info: XR17D152 UNIVERSAL 3.3V AND 5V PCI BUS DUAL UART JULY 2003 REV. 1.1.0 FEATURES GENERAL DESCRIPTION The XR17D1521 (D152) is a monolithic dual PCI Bus Universal Asynchronous Receiver and Transmitter (UART) in Exar’s PCI Bus UART family. The device is designed to meet today’s 32-bit PCI Bus and high

Divide by N Counter

Contextual Info: áç XR17C158 5V PCI BUS OCTAL UART MAY 2004 REV. 1.4.0 GENERAL DESCRIPTION The XR17C1581 158 is an octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication systems.

exar timer

Contextual Info: áç XR17C154 PRELIMINARY 5V PCI BUS QUAD UART APRIL 2001 REV. P1.0.0 GENERAL DESCRIPTION The XR17C1541 154 is a quad PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with same package and pin-out as the Exar XR17C158 octal UART. The device is designed to meet today’s

DAN119

Abstract: DIODE IT4 0x33F
Contextual Info: áç XR17C152 5V PCI BUS DUAL UART SEPTEMBER 2003 REV. 1.1.0 GENERAL DESCRIPTION The XR17C1521 152 is a monolithic dual PCI Bus Universal Asynchronous Receiver and Transmitter (UART) in Exar’s PCI Bus UART family. The device is designed to meet today’s 32-bit PCI Bus and high

Contextual Info: áç XR17C158 PCI BUS OCTAL UART AUGUST 2001 REV. 1.1.2 GENERAL DESCRIPTION The XR17C1581 158 is an octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication systems.

XR17C158

Contextual Info: áç XR17C158 5V PCI BUS OCTAL UART SEPTEMBER 2003 REV. 1.3.0 GENERAL DESCRIPTION The XR17C1581 158 is an octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication systems.

DIODE EFR 115

Contextual Info: XR17C158 PRELIMINARY PCI BUS OCTAL UART MARCH 2001 REV. 1.0.2 GENERAL DESCRIPTION The XR17C1581 158 is an octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication systems.

XC3030-70PC84C

Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 EP330PC XC3042-70PC84C A1020A-PL84C
Contextual Info: ULCt Cross-Reference Matra MHS Cross reference list of devices supported for ULC conversion is not exhaustiv as new devices are added regularly. Additional devices not shown in this list, may also be supported. MHS encourages you to contact your local TEMIC sales representative

QL4090

Abstract: pASIC 1 Family 160CQFP 208-CQFP
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

208CQFP

Contextual Info: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance

Contextual Info: QL4016 QuickRAM Data Sheet • • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density

Contextual Info: VAN T I S BE Y O N D PERFORMANCI-, Product Menu An AMD .om pan \ HIGHLIGHTS MACH 1 -5 CPLD Families Fastest speeds; Easiest-to-Use SpeedLocking (Fixed, Guaranteed Timing 3 2-51 2 Macrocells; 32-256 l/Os JTAG-ISP; 3 .3 -V or 5 -V Solutions PCI-Compliance at 5, 7, 10 and 12ns

Contextual Info: PRELIMINARY BEYOND PERFORMANCE VANTI S VF1 FIELD PROGRAMMABLE GATE ARRAY FEATURES AND BENEFITS ♦ The industry's first Variable-Grain-Architecture enables high-density, high-performance designs for a wide range of applications — Architecture adapts to logic to enable synthesis-friendly, high-performance designs

lt 7246

Contextual Info: AMDZ1 P R E L IM IN A R Y Am79C961 A PCnet -ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for the Industry Standard Architecture ISA and Extended Industry Standard Architecture (EISA) buses

teradyne z1890

Abstract: Sis 968 ispMACH 4000 development circuit gal amd 22v10 22v10 pal gal programming 22v10 Pal programming 22v10 272-BGA GAL programming PALCE* programming
Contextual Info: L A T T I C E S E M I C O N D U C T Programmable Logic Devices O R “A vision of the ultimate system — Lattice provides the tools and analog, digital, and everything in support necessary to utilize each between, instantly re-programmable.” of these building blocks. The

Integrated Development System

Abstract: puretech AT40K AT40KAL ATDH40M ATDM2100PC ATDM2100SN ATDS2100PC ATDS2100SN verilog code for routing table
Contextual Info: Contents Atmel FPGA Integrated Development System IDS contains the following items: • IDS Installation Guide • CD-ROM containing all necessary software and online documents Features • • • • • • • • • • • • • • • • •

syscon

Abstract: LFEC1E-3T100C ips works 6CW3
Contextual Info: LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported

sandisk micro sd

Abstract: digital clock using at89s52 microcontroller stepper motor control with avr application notes sandisk micro sd card pin configuration vhdl code for rs232 receiver STK 435 power amplifier Microcontroller AT89S52 vhdl code for ofdm Microcontroller AT89S52 40 pin fingerprint scanner circuit
Contextual Info: Atmel Corporation Atmel Operations Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 (408) 487-2600 Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1 (408) 441-0311 FAX 1 (408) 436-4314 Regional Headquarters Microcontrollers