CY7C164 Search Results

7C166

Abstract: C164 CY7C164 C1648 CY7C166 CY7C164-20PC CY7C164-20VC CY7C164-25PC CY7C164-25VC CY7C164-35PC
Contextual Info: CY7C164 CY7C166 16K x 4 Static RAM three-state drivers. The CY7C166 has an active low output enable OE feature. Both devices have an automatic power-down feature, reducing the power consumption by 65% when deselected. Features • High speed — 15 ns Output

a13c

Abstract: 7C166 CY7C164 CY7C166 7C166-20 CY7C164-12VC 7C164-12 7C164 CY7C164-20PC
Contextual Info: CY7C164 CY7C166 m 'w CYPRESS 16K x 4 Static RAM Features Functional Description • High speed — 15 ns T he CY7C164 and CY7C166 are high-per­ form ance CMOS static RAM s organized as 16,384 by 4 bits. Easy mem ory expan­ sion is provided by an active LO W chip en­

Contextual Info: CY7C1643KV18/CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features • Offered in both Pb-free and non Pb-free packages Separate independent read and write data ports

CY7C1645KV18-450BZXI

Abstract: 3M Touch Systems
Contextual Info: CY7C1641KV18, CY7C1656KV18 CY7C1643KV18, CY7C1645KV18 144-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit QDR ® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports

TAA 691

Abstract: C1648 CY7C164 CY7C166 C1649 1709 013 c164 7C166 CY7C164-25 CY7C166-15
Contextual Info: CY7C164 CY7C166 16K x 4 Static RAM Features Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable CE and tri-state drivers. The CY7C166 has an active LOW Output

cmos SRAM 35ns 8k X 8 dip

Abstract: 7C166 CY7C161 CY7C162 CY7C164 CY7C166 CY7C185 CY7C186 CY7C187 7C164
Contextual Info: Qualification Report January 1992 QTP 91094 64K SRAM FAMILY MARKETIN G DEVICE PART NBR DESCRIPTION CY7C161 16K x 4 SIO CY7C162 16K x 4 (SIO) CY7C164 16K x 4 CY7C166 (OE) CY7C185 8K x 8 CY7C186 8K x 8 (.6 DIP) CY7C187 64K x 1 Version 1.2 PRODUCT DESCRIPTION (for qualification)

3M Touch Systems

Contextual Info: CY7C1646KV18, CY7C1657KV18 CY7C1648KV18, CY7C1650KV18 144-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 144-Mbit density (16 M x 8, 16 M × 9, 8 M × 18, 4 M × 36)

Contextual Info: CY7C1643KV18, CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features • Offered in both Pb-free and non Pb-free packages Separate independent read and write data ports

CY7C1643KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C1643KV18, CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features • Offered in both Pb-free and non Pb-free packages Separate independent read and write data ports

C1645

Abstract: CY7C166-15PC CY7C164 CY7C166 7C166 C164 C166 CY7C164-20PC CY7C164-20VC CY7C164-25PC
Contextual Info: 66 CY7C164 CY7C166 16K x 4 Static RAM Features three-state drivers. The CY7C166 has an active LOW Output Enable OE feature. Both devices have an automatic powerdown feature, reducing the power consumption by 65% when deselected. • High speed — 15 ns

Cypress 7C166

Abstract: 7c166 CY7C164-15PC C164 CY7C164 CY7C166 CY7C164-20PC CY7C164-20VC CY7C164-25PC CY7C164-25VC
Contextual Info: 1CY 7C16 6 CY7C164 CY7C166 16K x 4 Static RAM three-state drivers. The CY7C166 has an active low output enable OE feature. Both devices have an automatic power-down feature, reducing the power consumption by 65% when deselected. Features • High speed — 15 ns

Contextual Info: CY7C164A CY7C166A CYPRESS SEMICONDUCTOR Features 16,384 x 4 Static R/W RAM through I/O3 is written into the memory location specified on the address pins Ao The CY7C164A and CY7C166A are high- through A 13). performance CMOS static RAMs orga­ nized as 16,384 by 4 bits. Easy memory ex­ Reading the device is accomplished by tak­

Contextual Info: CY7C164A CY7C166A 16,384 x 4 Static R/W RAM CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Output Enable OE feature (7C166A) • CMOS for optimum speed/power • High speed - 15 ns t*A • Low active power - 550 mW • Low standby power

Contextual Info: CY7C164A _ CY7C166A SEMICONDUCTOR 16,384 x 4 Static R/W RAM Features Functional Description • Automatic power-down when deselected The CY7C164A and CY7C166A are highperformance CMOS static RAMs orga­ nized as 16,384 by 4 bits. Easy memory ex­

Contextual Info: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement

C1647

Abstract: C164 C1648 CY7C164 CY7C166 7c164-15 C1649 7C166-20 C1646 7C166
Contextual Info: CY7C164 CY7C166 16K x 4 Static RAM Features three-state drivers. The CY7C166 has an active LOW Output Enable OE feature. Both devices have an automatic powerdown feature, reducing the power consumption by 65% when deselected. • High speed — 15 ns Output

Contextual Info: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement

Contextual Info: CY7C164A CY7C166A 16Kx 4 Static RAM Features Functional Description • High speed — 20 ns • Output enable OE feature (7C166A) • CMOS for optimum speed/power • Low active power — 550 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs

C1647

Abstract: C1649 C1645 CY7C164-20PC CY7C164-20VC CY7C164-25PC CY7C164-25VC CY7C164-35PC CY7C164 CY7C166
Contextual Info: CY7C164 CY7C166 16K x 4 Static RAM Features three-state drivers. The CY7C166 has an active LOW Output Enable OE feature. Both devices have an automatic powerdown feature, reducing the power consumption by 65% when deselected. • High speed — 15 ns Output

C164A-2

Abstract: CY7C164A CY7C166A 2102 ram AM716
Contextual Info: CY7C164A CY7C166A '# CYPRESS 16K x 4 Static RAM Features Functional D escription • High speed — 20 ns • Output enable OE feature (7C166A) • CMOS for optimum speed/power • Low active power — 550 raW • Low standby power — 220 raW • TTL-compatible inputs and outputs

CY7C164-35PC

Abstract: CY7C164-20PC CY7C164-15LC CY7C164-20VC CY7C164-20DC CY7C164-20LC CY7C164-25PC CY7C164-25VC 7C164-25DC CY7C164
Contextual Info: CY7C164 CY7C166 CYPRESS SEMICONDUCTOR 16,384 x 4 Static R/W RAM Features Functional Description • Automatic power-down when deselected • Output Enable OE feature (7C166) • CMOS for optimum speed/power • High speed — Iaa = 15 ns • Low active power

3M Touch Systems

Contextual Info: CY7C1643KV18, CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features • Offered in both Pb-free and non Pb-free packages Separate independent read and write data ports

3M Touch Systems

Contextual Info: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement

5 pin A13E

Abstract: A12E 7C166 Cypress 7C166 7c164-15 7C164-12 7C164 a13e
Contextual Info: CY7C164 CY7C166 Ì CYPRESS SEMICONDUCTOR 16Kx 4 Static RAM Features Functional Description • High speed — IS ns The CY7C164and CY7C166 are high-per­ formance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expan­ sion is provided by an active LOW chip en­