CY7C162 Search Results

CY7C161

Abstract: CY7C162 C1624
Contextual Info: CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.

7cl6

Abstract: D-2501 CY7C161A CY7C162 CY7C162A
Contextual Info: CYPRESS SEMICONDUCTOR 4bE » B SSfl'lbfe.S □ QQbMSb b q c y p CY7C161A CY7C162A • - j/ "— = 16,384 x 4 Static RAV RAM Separate I/O SEMICONDUCTOR Features • Automatic power-down when dese­ lected • Transparent write 7C161A • CMOS for optimum speed/power

CY7C1620KV18-250BZXC

Contextual Info: CY7C1618KV18, CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18, 8 M × 36 CY7C1618KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth

C1623

Abstract: C1624 c162 c1627 C1622 CY7C161 CY7C162 C1628 C1625
Contextual Info: 1CY 7C16 2 CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.

Contextual Info: CY7C161 CY7C162 16Kx 4 Static RAM with Separate I/O Features into the memory location specified on the address pins Ao through A13 . Reading the device is accomplished by tak­ ing the chip enables (CEi, CE2) LOW while write enable (WE) remains HIGH. Under these conditions the contents of the

cmos SRAM 35ns 8k X 8 dip

Abstract: 7C166 CY7C161 CY7C162 CY7C164 CY7C166 CY7C185 CY7C186 CY7C187 7C164
Contextual Info: Qualification Report January 1992 QTP 91094 64K SRAM FAMILY MARKETIN G DEVICE PART NBR DESCRIPTION CY7C161 16K x 4 SIO CY7C162 16K x 4 (SIO) CY7C164 16K x 4 CY7C166 (OE) CY7C185 8K x 8 CY7C186 8K x 8 (.6 DIP) CY7C187 64K x 1 Version 1.2 PRODUCT DESCRIPTION (for qualification)

ID14771

Abstract: C1626 A10C A12C CY7C161 CY7C162 V21 PACKAGE DIAGRAM
Contextual Info: CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O CYPRESS Features • High speed — 15-ns • Transparent write 7C161 • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 220 mW • TTL compatible inputs and outputs

Contextual Info: CY7C161A CY7C162A CYPRESS SEMICONDUCTOR Features • Automatic power-down when dese­ lected • T ransparent write 7C161A • CMOS for optim um speed/power • High speed - 15 ns t* • Low active power - 550 mW • Low standby power - 220 mW • TTL-compatible inputs and outputs

CY7C161A

Abstract: CY7C162A A5624 cy7c161a-35dmb
Contextual Info: CY7C161A CY7C162A 16KĂxĂ4 Static RAM with Separate I/O into the memory location specified on the Features Functional Description D The CY7C161A and CY7C162A are highĆ performance CMOS static RAMs orgaĆ nizes as 16,384 by 4 bits with separate I/O. Easy memory expansion is provided by acĆ

C1623

Abstract: C1624 C1627 C1622 c1628 C162 CY7C161 CY7C162 7C162 C1625
Contextual Info: CY7C161 CY7C162 16KĂxĂ4 Static RAM with Separate I/O Features Functional Description D The CY7C161 and CY7C162 are highĆperĆ formance CMOS static RAMs organized as 16,384 by 4 bits with separate I/O. Easy memory expansion is provided by active LOW chip enables CE1, CE2 and threeĆ

Contextual Info: CY7C161A CY7C162A CYPRESS SEMICONDUCTOR Features Functional Description • High speed The CY7C161A and CY7C162A are highperformance CMOS static RAMs orga­ nizes as 16,384 by 4 bits with separate I/O. Easy memory expansion is provided by ac­ tive LOW chip enables C E i, CE2 and

CY7C161

Abstract: CY7C162 CY7C162-25VC
Contextual Info: CY7C161 CY7C162 16K x 4 Static RAM with Separate I/O CYPRESS Features • High speed — 15-ns • Transparent write 7C161 • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 220 mW • TTL compatible inputs and outputs

Contextual Info: CY7C1618KV18, CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18, 8 M × 36 CY7C1618KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth

Contextual Info: CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit QDR II SRAM 2-Word Burst Architecture 144-Mbit QDR ® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9

3M Touch Systems

Contextual Info: CY7C1623KV18 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18 CY7C1623KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth Functional Description

Contextual Info: CY7C161A CY7C162A CYPRESS SEMICONDUCTOR 16K x 4 Static RAM Separate I/O Features Functional Description • High speed The C Y 7C161A and C Y 7C162A are highperform ance C M O S static R A M s orga­ nizes as 16,384 by 4 bits w ith sep a ra te I/O . Easy m em ory expansion is provided by ac­

Contextual Info: CY7C161 CY7C162 CYPRESS SEMICONDUCTOR Features Functional Description • High speed — 15-ns T he CY7C161 an d CY 7C162 are high-per­ form ance C M O S static R A M s organized as 16,384 by 4 bits w ith sep a ra te I/O . Easy m em ory expansion is provided by active

CY7C161A

Abstract: CY7C162A
Contextual Info: CY7C161A CY7C162A 16K x 4 Static RAM with Separate I/O Features Easy memory expansion is provided by active LOW chip enables CE1, CE2 and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 60% when deselected.

Contextual Info: CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture 144-Mbit QDR ® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9

CY7C1614KV18

Abstract: CY7C1612KV18-300BZXI CY7C1614KV18-250BZXC CY7C1612KV18
Contextual Info: CY7C1610KV18, CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 ADVANCE INFORMATION 144-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth

CY7C1614KV18

Abstract: CY7C1612KV18-300BZXI
Contextual Info: CY7C1610KV18, CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit QDR II SRAM 2-Word Burst Architecture 144-Mbit QDR ® II SRAM 2-Word Burst Architecture Features Configuration Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1611KV18, CY7C1626KV18 CY7C1613KV18, CY7C1615KV18 144-Mbit QDR II SRAM 4-Word Burst Architecture 144-Mbit QDR ® II SRAM 4-Word Burst Architecture Features Configuration Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: CY7C1616KV18, CY7C1627KV18 CY7C1618KV18, CY7C1620KV18 144-Mbit DDR II SRAM 2-Word Burst Architecture 144-Mbit DDR II SRAM 2-Word Burst Architecture Features Configuration • 144-Mbit density 16 M x 8, 16 M × 9, 8 M × 18, 8 M × 36 CY7C1616KV18 – 16 M × 8

Contextual Info: CY7C161 CY7C162 CYPRESS Features • High speed — 15-ns • Transparent write 7C16I • CMOS for optimum speed/power • Low active power — 633 mW • Low standby power — 220 mW • TTL compatible inputs and outputs • Automatic power-down when deselected