CONFIG Search Results

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: S E M I C O N D U C T O R , AND NETWORKING Section 2 - Data Sheets Data Sheets COMPUTING I N C GA1000 Custom Clock Generator. 2-3 GA1085 11-Output Configurable Clock B uffe r. 2-19

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

74AC11520

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations

2a117

Contextual Info: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

2N404

Abstract: MPS404 2n404a a5t404
Contextual Info: TYPES A5T404, A5T404A, A8T404, A8T404A P-N-P SILICON TRANSISTORS _B U L L E T I N N O . O L -S 7 3 1 1 9 7 9 , M A R C H 1973 SILECTt TRANSISTORS* FOR LOW-COST REPLACEMENT OF GERMANIUM 2N404, 2N404A • A5T404, A5T404A Have Standard TO-18 100-mil Pin-Circle Configuration

Contextual Info: 74ACT11132 QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCAS177 - D3974, JANUARY 1992 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Center-Pin V^c and GND Pin Configurations Minimize High-Speed Switching Noise EP/C Enhanced-Performance Implanted

Contextual Info: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to

TLP570

Abstract: tlp371
Contextual Info: F7 Typa No. Pin Configuration TLP371 TLP372 Features CTR % eiF Min. im A l V c e c d (V) Safety Standard (Note 2) (V) BVs (Vrms) 100 300 5,000 O 1.2 100 35 2,500 o 1.2 100 300 5,000 o eie Max. (mA) 1,000 1.2 1,000 1,000 VCEO UL TClV VDE BSI High V ceo (300V)

TI009

Contextual Info: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

RAV 14202

Abstract: TMS320C26
Contextual Info: SMJ320C26 DIGITAL SIGNAL PROCESSOR 68-P IN GB PIN G R ID A R R A Y C E R A M IC P A C K A G E t TO P V IE W 100-ns Instruction Cycle Time 1568 Words of Configurable On-Chip Data/Program RAM 1 2 3 4 5 6 7 6 9 10 11 256 Words of On-Chip Program ROM 128k Words of Data/Program Space

D2957

Abstract: 1987-REVISEDAPRIL
Contextual Info: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted

74AC108

Abstract: so 54 t 74AC11066
Contextual Info: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to

Contextual Info: PAL20L8A, PAL20R4A, PAL20R6A, PAL20R8A STANDARD HIGH-SPEED PAL CIRCUITS D 2 7 0 6 , DEC EM BE R 1 9 8 2 - R E V IS E D DEC EM BE R 1 9 8 7 PAL20L8' M SUFFIX . . . JW PACKAGE C SUFFIX . . . JW OR NT PACKAGE Standard High Speed 25 ns PAL Family • Choice of Input/Output Configuration

74690

Abstract: 74692 8Q21
Contextual Info: TFyAi TNSTR LOGIC T EX A S I N S T R { L O G I C ! 1 1 91D 74690 D T-5£-0? D E | 0 ^ 1 7 2 3 DD74h1G 5 1 ~ SN 74 A S 18 2 3 9-BIT BUS INTER FA CE FLIP-FLUPS WITH 3-STATE OUTPUTS APRIL 1 9 8 7 NT PACKAGE Center V q c ar|d GND Configuration Provides Minimum Lead Inductance in High

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS378-APRIL 1994 ' Low Output Skew for Clock-Distribution and Clock-Generation Applications DL PACKAGE TOP VIEW * Operates at 3.3-V Vcc u ’ Distributes One Clock Input to Six Outputs ' One Select Input Configures Up to Three

sn74as306

Contextual Info: SN74AS305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER D3SM, JUNE 1990 - REVISED SEPTEMBER 1990 Maximum Output Skew of 1 ns D OR N PACKAGE {TOP VIEW Maximum Pulse Skew of 1 n* 03 [ Center Pin Vcc and GND Configurations Minimize High-Speed Switching Noise U 04 [ 2

Contextual Info: TOSHIBA TC4W53F/FU TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4W53F, TC4W53FU 2-CHANNEL MULTIPLEXER / DEMALTIPLEXER The TC4W53 is multiplexer with capabilities of selection and mixture of analog signal and digital signal. TC4W53F has 2 channel configuration.

Contextual Info: SN74AS305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER D3596, JUNE 1990 D OR N PACKAGE CTOP VIEW Maximum Output Skew of 1 ns Maximum Pulse Skew of 1 ns Center Pin Vc c and GND Configurations Minimize High-Speed Switching Noise Package Options Include Plastic “Small

SBP 9900

Abstract: SBP9989
Contextual Info: SBP 9960 SBP9960 PR O G R A M M A B LE CRU I/O EXPANDER 1.0 INTRODUCTION 1.1 GENERAL DESCRIPTION The SBP 9960 Programmable CRU I/O Expander is a ruggedized m onolithic software-configurable input/output device fabricated w ith oxide separated Integrated Injection Logic |2 l technology. The

PD4A

Contextual Info: _ bq3285 UIMITRODE- Real-Time Clock RTC Features >• Direct clock/calendar replace­ ment for IBM AT-compatible computers and other applications >- Functionally compatible with the DS1285 ~ Closely matches MC146818A pin configuration >• 114 bytes of general nonvolatile