PLH22 Search Results

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS378-APRIL 1994 ' Low Output Skew for Clock-Distribution and Clock-Generation Applications DL PACKAGE TOP VIEW * Operates at 3.3-V Vcc u ’ Distributes One Clock Input to Six Outputs ' One Select Input Configures Up to Three

CDC2586

Abstract: CDC586
Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SC A S 337- FEBRUARY 1993 - REVISED MARCH 1994 Edge-Triggered Clear for Half-Frequency Outputs TTL-Compatible Inputs and Outputs Outputs Have Internal 26-Q Series Resistors to Dampen Transmission Line

Contextual Info: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379 - FEBRUARY 1993 - REVISED MARCH 1994 Application for Synchronous DRAMs Outputs Have Internal 26-Q Series Resistors To Dampen Transmission Line Effects Edge-Triggered Clear for Half-Frequency

Contextual Info: CDC2536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _SCAS3 7 7 - APRIL 1994 D L PACKAGE TOP VIEW 1 U 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 description

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS337 - FEBRUARY 1993 - REVISED MARCH 1994 * Edge-Triggered Clear for Half-Frequency Outputs * TTL-Compatible Inputs and Outputs * Outputs Have Internal 26-Q Series Resistors to Dampen Transmission Line

Contextual Info: CDC586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS336 - FEBRUARY 1993 - REVISED MARCH 1994 • ■ * Low Output Skew for Clock-Dlstribution and Clock-Generation Applications * Application for Synchronous DRAM, High-Speed Microprocessor

CDC536

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS378 - APRIL 1994 DL PACKAGE TOP VIEW 1 u 28 2 27 3 26 4 25 5 24 6 23 7 22

3 phase waveform generator

Abstract: CDC2536
Contextual Info: CDC2536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS377 - APRIL 1994 DL PACKAGE TOP VIEW 1 2 3 4 5 6 8 9 10 11 12 13 14 u 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Distributed Vcc and Ground Pins Reduce Switching Noise Packaged in Platic 28-Pin Shrink Small

CDC586

Contextual Info: CDC586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS S C A S 336- FEBRUARY 1993 - REVISED MARCH 1994 Application for Synchronous DRAM, High-Speed Microprocessor Edge-Triggered Clear for Half-Frequency Outputs TTL-Compatible Inputs and Outputs Outputs Drive 50-Q Parallel-Terminated

Contextual Info: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379 - FEBRUARY 1993 - REVISED MARCH 1994 Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V V cc Distributes Differential LVPECL Clock

Contextual Info: CDC586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336 - FEBRUARY 1993 - REVISED MARCH 1994 Low Output Skew for Clock-Distribution and Clock-Generation Applications Application for Synchronous DRAM, High-Speed Microprocessor Operates at 3.3-V Vc c

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337-FEBRUARY 1993 - REVISED MARCH 1994 Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V Vcc Distributes One Clock Input to Twelve Outputs Two Select Inputs Configure Up to Nine

diode sy 170/10

Abstract: Z80A sti "General Instrument" DO-7 Diode Marking Z80A DMA pes 5003 p type iii z80a-dma ilo1
Contextual Info: MIL-M-38510/482A{USAF 18 June 1984 QUALIFICATION REQUIREMENTS REMOVED SUPERSEDING!-MIL-M-38510/482 USAF) 16 M a r c h 1982 MILITARY MICROCIRCUITS, MONOLITHIC I INACTIVE SPECIFICATION DIGITAL, N-CHANNEL, DIRECT MEMORY ACCE SS FOR NEW DESIGN AFTER