GA1085 Search Results

Contextual Info: S E M I C O N D U C T O R , AND NETWORKING Section 2 - Data Sheets Data Sheets COMPUTING I N C GA1000 Custom Clock Generator. 2-3 GA1085 11-Output Configurable Clock B uffe r. 2-19

2t smd

Abstract: ebe switches fbln GA1085 GA1085-MC1000 GA1085-MC500 PS1000
Contextual Info: C O M P U T I N G A N D N E T W O R K I N G Figure 1. Block Diagram FBIN rrn TEST VDD QO GND Q1 Q2 VD D E­ E E E E E S1 GA1085 R EFC LK n o i n n SO rtn F1 n n FO n n GND n r T \ VD D Phase Detector Q10 Phase Select VCO Q9 11-Output Configurable Clock Buffer

Contextual Info: COMPUTING AND N E T WO RKI N G GA1085 Figure 1. Block Diagram FBIN S1 R EFC LK SO I T T I f T Ò I |~ 9 ~ | f s l TT TEST E F1 FO |~ T | m GND [~5 VDD Phase Detector VDD 13 QO GND Q1 Q2 Q10 E E EE Phase Select VCO 3 09 11-Output Configurable Clock Buffer GND

Contextual Info: T R I Q i! I N T S E M I C O N D U C T O R , I N C 7 Q $ f COM PUTING AND NETWORKING Figu re 1 . Block D iagram FBIN S1 GA1085 REFC LK SO F1 FO GND Data Sheets 11-Output Configurable Clock Buffer Features • Wide frequency range: 24 MHz to 105 MHz GND Q3

Contextual Info: ff / il ! r'¡ S E M I C O N D U C T O ! F; , I N C 7 COMPUTING AND NETWORK N G Figure 1. Block Diagram FBIN SI GA1085 R EFC LK SO F1 FO GND i~ñ~i [T5~i 1 9 11~81rn [~t] fr VD D Phase Delectar VDD Q 10 Phase Select VCO OO G ND Q9 E G ND Divide Logic r 4 , -r5, or *6

Contextual Info: Section 2 •Data Sheets GA1085 11-Output Configurable Clock B u ffe r. 2-3 GA1087 11-Output Configurable Clock B u ffe r. 2-13 GA1088 11-Output Configurable Clock B u ffe r. 2-23

GA1085

Abstract: GA1085-MC1000
Contextual Info: R I Q U I N T S E M I C O N D U C T O R, I N C . GA1085 Figure 1. Block Diagram FBIN S1 REFCLK S0 F1 F0 GND 11 10 9 8 7 6 5 TEST 12 4 VDD Phase Detector VDD 13 Phase Select VCO Q0 14 MUX GND 15 Q1 16 Q2 17 VDD 18 Q10 2 Q9 1 GND Divide Logic ÷4, ÷5, or ÷6

T80-6

Abstract: GA1085 GA1085-MC1000 Q9100
Contextual Info: T R I Q U I N S E M I C O N D U C T O R , I N C T TO SI Fig u re 1. B lock D ia g ra m GA1085 rrnnn m rii rn m FBIN TEST VDD 00 GND Q1 Q2 VDD E E E E E E E S1 REFCLK SO F1 FO GND 11-Output Configurable Clock Buffer Tj VDD \ Phase Detector Phase Select VCO

NEC 2532

Abstract: cache controller intel 82496 Voltage Doubler with 555 circuit ICS2686 AP-453 82491 IC 7418 intel 82496 TTL 7400 national semiconductor 241563
Contextual Info: AP-479 APPLICATION NOTE Pentium Processor Clock Design November 1995 Order Number 241574-002 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in

Contextual Info: R I T Q O U I N T S E M I C O N D U C T O R , I N C G A1085 Figure 1. Block Diagram FBIN S1 RE FC LK SO F1 FO 11-Output GND n n n r i n n f s i 171 le 3 T E ST |^12 VDD QO GND Q1 Q2 VDD Phase Detector F E I» E E E Phase Select V DD •3 ■3 Q10 Configurable

Contextual Info: /: S // I FO GND G C /v u Figure 1. Block Diagram F B IN TEST VOD QO GND Q1 Q2 VDD S1 SO F1 w 3 Phase Detector VDD 010 Phase Select VCO 09 I L r , i a L 11-Output Configurable Clock Buffer GND Divide Logic +5, or *6 E 08 t4 , Features * Group B 03 27 Output Butters j Gr£up

Contextual Info: PRELIMINARY COM P U TIN G AND NETWORKING Figure 1. Block Diagram FBIN GND R EFC LK GND GA1089 GND GND GND 11-Output Configurable Clock Buffer Features * * Wide frequency range: 65 MHz to 90 MHz and 130 MHz to 180 MHz Output configurations: 8 outputs at fref

Contextual Info: I Q 7 S U I N S E M I C O N D U C T O R , I N C T Figure 1. Block Diagram FBIN G A 1085 S1 R EFCLK itti nói TEST VDD OD GND Q1 Q2 VDD E E E E E E E SO m i e i F1 FO GND r n m nr 3 Phase Detector VDD •3 ■3 010 Phase Se lect VCO Q9 3 D ivide lo g ic +4, +5, or +6