74AC11002 Search Results

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES ăą SCAS024A − JUNE 1987 − REVISED APRIL 1993 • • • • • 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration

54AC11002

Abstract: 74AC 74AC11002 D2957 11002
Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES TI0042— 0 2 9 5 7 , JU N E 1987— R EVISED M ARCH 1990 Row-Through Architecture to Optimize PCB Layout 5 4 A C 1 1002 . . . J P ACKA G E 74A C 11 0 02 . . . D O R N P A C K A G E TO P V IE W Center-Pin V c c and GND Configurations to

5V 2A SW regulator

Abstract: 54AC11002 74AC11002
Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS024A – JUNE 1987 – REVISED APRIL 1993 • • • • • 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES TI0042— 0 2 9 5 7 . JU NE 1907— REVISED MARCH 1990 • Flow-Through Architecture to Optimize PCB Layout 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to

54AC11002

Abstract: 74AC11002
Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2ĆINPUT POSITIVEĆNOR GATES ăą SCAS024A − JUNE 1987 − REVISED APRIL 1993 • • • • • 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration

54AC11002

Abstract: 74AC11002
Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS024A – JUNE 1987 – REVISED APRIL 1993 • • • • • 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration

Contextual Info: SAMSUNG ELECTRONICS INC b?E T> 7 *îb4 m s 0P17S1S bSO • SMGK PRELIMINARY BiCMOS SRAM KM68B261A ABSOLUTE MAXIMUM RATINGS* Item Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to VSs Power Dissipation Storage Temperature Operating Temperature

FT 4013 d dual flip flop

Abstract: FT 4013 D flip flop 74HC octal bidirectional latch 74HCT 4013 DATASHEET 4511 pin configuration SN7432 fairchild CMOS TTL Logic Family Specifications 7805 acv Datasheet of decade counter CD 4017 sn74154
Contextual Info: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX

T flip flop IC

Abstract: pin designation for CD40110B IC 74LS series logic gates 3 input or gate FT 4013 d dual flip flop ic cmos 4011 CD4001* using NAND gates IC CD 4033 pin configuration Quad 2 input nand gate cd 4093 FT 4013 D flip flop 74HCT 4013 DATASHEET
Contextual Info: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX

ACT11002

Abstract: T11002
Contextual Info: 74AC/ACT 11002 Signetics Quad 2-Input NOR Gate Product Specification ACL Products GENERAL INFORMATION FEATURES C O N D IT IO N S T . = 25°C ; G N D = 0V; • Output capability: ±24 mA • CMOS AC and TTL (ACT) voltage level inputs • SOn Incident wave switching