CML ECL TERMINATION Search Results

CML ECL termination

Abstract: dj rm RJ12 RJ22
Contextual Info: I/O Structures and Jitter Presentation 1 RELATIVE SIGNAL SWINGS AND LEVELS PECL 4V “5V ECL” CML 3.3V 3V CML (2.5V) LVPECL 2V LVPECL LVDS -1V -2V CML (1.2V) “3V ECL” 1V 0V CML (1.8V) Referenced to Ground “2.5V ECL” ECL Older Technology - Rarely seen

KPT21

Abstract: MC100EPT21 2x2 dfn
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT21

Abstract: MC100EPT21 KA21
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

MC100EPT21DG

Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT23

Abstract: EPT23 MC100EPT23 VDFN-8 mc100ept23dg
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

EPT23

Abstract: KPT23 MC100EPT23 2x2 dfn
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

485G

Abstract: NB7L32M MARKING 224 QFN-16
Contextual Info: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Descriptions The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The

485G

Abstract: NB7L32M
Contextual Info: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The

CML ECL termination

Abstract: MC100EP16 MC100EP16F MC100EP16VS MC100EP16VT MC100LVEP16 MC10EP16 MC10EP16T MC10LVEP16 NBSG16
Contextual Info: SGD508/D Jan-2002 Rev 0 1 to 12 GHz Differential Receiver/Drivers Bandwidth GHz Gain Input Termination (50Ω) Open Input Default State (D, D) Input Level Output Level Output Enable LOW, HIGH ECL, CMOS, CML, LVDS RSECL(3) No 1 FCBGA 16 Yes(1) LOW, HIGH ECL, CMOS,

Contextual Info: Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM VCCI VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VCCO ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VEE VTN TERMINATION LE INPUT HYS

ADCMP580

Abstract: ADCMP581 ADCMP582 MO-220-VEED-2 PRBS31 ADCMP582BCP-R2 CP-16-3 VCCO11
Contextual Info: Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM VCCI VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VCCO ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VEE VTN TERMINATION LE INPUT HYS

MAX3910

Abstract: MAX3935 MAX3935EGJ STM-64
Contextual Info: 19-4803; Rev 0; 4/01 10.7Gbps EAM Driver Features ♦ Single -5.2V Power Supply The MAX3935 accepts differential ECL or ground-referenced CML clock and data-input signals. Inputs are terminated with on-chip 50Ω resistors. An input-data retiming latch can be used to reject input-patterndependent jitter if a clock signal is available.

SY89872U

Abstract: SY89873L SY89874U SY89875U SY89876L CML Vt 1999 50 Ohm CML ECL termination tf350
Contextual Info: The “Any-In” Advantage and what is RPE, FSI, Crosstalk Elimination Micrel Internal Termination “ANY-In” 1 Precision Edge Patented Designs “Any-In” is simple Internal Termination Improves Jitter Performance Simplifies Designs Eliminates external components

4x4 mlf

Abstract: 100EPT23 100EPT23L SY89222L 100EPT21 SY58017 SY58011U SY58012U SY58013U SY58021U
Contextual Info: Micrel Precision Edge Timing and Distribution Reference Guide Clock Distribution Part Number Fanout Input Output Voltage Max. Freq. GHz Package Description SY54011R New! 1:2 ANY CML 1.2/1.8V 3.2 MLF-16 Low Voltage CML Fanout Buffer/Translator. SY56011R New!

Contextual Info: FEATURES 150 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input risetime bandwidth 100 ps minimum pulse width 35 ps typical output rise/fall −2 V to +3 V input range with +5 V/−5.2 V supplies On-chip terminations at both input pins

HM3500

Contextual Info: HONEYüJELL D I G I T A L P R O D U C T bt De | 4 S S m S 3 □□0DD73 7 | T-42-11-15 MAY 1985 HM3500 ECL/TTL GATE ARRAY PRELIMINARY PRODUCT DESCRIPTION The HM3500 Figure 1 is a 400 picosecond, 3500 equivalent gate density VLSI monolithic integrated circuit using Honeywell’s ADB-II fabrication process.

transistor a473

Abstract: A473 transistor conhex chip die npn transistor CML ECL compatible
Contextual Info: HONEYWELL "DIGITAL PRODUCT bt. dË | MSS1M5B ODOOOEt. T f' T-42-11-13 MARCH 1985 ECL GATE ARRAY HE2000 PRODUCT DESCRIPTION The HE2000 Gate Array Figure 1 is a 300 picosecond, 2000 equivalent gate density Very Large Scale Integration (VLSI) monolithic integrated circuit built using Honeywell’s

64 PIN CERDIP

Contextual Info: HONEYWELL DIGITAL PRODUCT bb D E * 4SS14S3 0000050 b • ■ ■ RAD HARD ECL/TTL GATE ARRAY PRODUCT DESCRIPTION The HM1000R Gate Array Figure 1 is an 800 pico­ second, 1000 equivalent gate density LSI monolithic integrated circuit built using Honeywell’s radiation

16 pins qfn 3x3 footprint

Abstract: 485G AND8020 NB7L86M NB7L86MMN NB7L86MMNG
Contextual Info: NB7L86M 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination The NB7L86M is a multi−function differential Logic Gate, which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high

Contextual Info: NB7L86M 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination The NB7L86M is a multi−function differential Logic Gate, which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high

485G

Abstract: NB7L216 NB7L216MN NB7L216MNG NBSG16
Contextual Info: NB7L216 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB7L216 is a differential receiver/driver with high gain output targeted for high frequency applications. The device is functionally

485G

Abstract: NB7L216 NB7L216MN NB7L216MNG NBSG16 649E-09
Contextual Info: NB7L216 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination The NB7L216 is a differential receiver/driver with high gain output targeted for high frequency applications. The device is functionally

mic5380

Abstract: nu-horizons KSZ8863 KSZ8863MLL KSZ9021RN PQFP-128 footprint KSZ8863MLL EVAL KSZ8851SNL SFP EVAL BOARD MIC26950
Contextual Info: Shortform Catalog July 2010 Shortform Catalog July 2010 2010 Micrel, Inc. The information furnished by Micrel, Inc., in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use, nor any infringements of patents

Contextual Info: Shortform Catalog September 2011 2011 Micrel, Inc. The information furnished by Micrel, Inc., in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use, nor any infringements of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of Micrel, Inc. Micrel reserves the right to change circuitry