CML ECL TERMINATION Search Results

CML ECL termination

Abstract: dj rm RJ12 RJ22
Contextual Info: I/O Structures and Jitter Presentation 1 RELATIVE SIGNAL SWINGS AND LEVELS PECL 4V “5V ECL” CML 3.3V 3V CML (2.5V) LVPECL 2V LVPECL LVDS -1V -2V CML (1.2V) “3V ECL” 1V 0V CML (1.8V) Referenced to Ground “2.5V ECL” ECL Older Technology - Rarely seen

CML ECL termination

Abstract: AND8173 AND8020
Contextual Info: AND8173/D Termination and Interface of On Semiconductor ECL Devices With CML Current Mode Logic OUTPUT Structure http://onsemi.com APPLICATION NOTE By Paul Shockman Contents SECTION 1.UNLOADED CML VOLTAGE LEVELS (DC OPEN) SECTION 2.DIRECT CONNECT (DC) CML LOAD

AND8020

Abstract: CML ECL termination Z0 127 TRANSISTOR equivalent
Contextual Info: AND8173/D Termination and Interface of ON Semiconductor ECL Devices With CML Current Mode Logic OUTPUT Structure http://onsemi.com APPLICATION NOTE By Paul Shockman Introduction Contents SECTION 1.UNLOADED CML VOLTAGE LEVELS (DC OPEN) SECTION 2.DIRECT CONNECT (DC) CML LOAD

KPT21

Abstract: MC100EPT21 2x2 dfn
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT21

Abstract: MC100EPT21 KA21
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

MC100EPT21DG

Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT21

Abstract: MC100EPT21
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT21

Abstract: MC100EPT21
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT21

Abstract: MC100EPT21
Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT23

Abstract: EPT23 MC100EPT23 VDFN-8 mc100ept23dg
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

EPT23

Abstract: KPT23 MC100EPT23 2x2 dfn
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT23

Abstract: EPT23 MC100EPT23
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

Contextual Info: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The

Contextual Info: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The

485G

Abstract: NB7L32M
Contextual Info: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The

CML ECL termination

Abstract: MC100EP16 MC100EP16F MC100EP16VS MC100EP16VT MC100LVEP16 MC10EP16 MC10EP16T MC10LVEP16 NBSG16
Contextual Info: SGD508/D Jan-2002 Rev 0 1 to 12 GHz Differential Receiver/Drivers Bandwidth GHz Gain Input Termination (50Ω) Open Input Default State (D, D) Input Level Output Level Output Enable LOW, HIGH ECL, CMOS, CML, LVDS RSECL(3) No 1 FCBGA 16 Yes(1) LOW, HIGH ECL, CMOS,

package marking 504c

Abstract: ICS853S 853S310CVILF
Contextual Info: Low Skew, 1-to-8 Differential-to3.3V LVPECL/ECL Fanout Buffer ICS853S310I DATA SHEET General Description Features The ICS853S310I is a low skew, high performance 1-to-8 Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL

Contextual Info: Low Skew, 1-to-8 Differential-to3.3V LVPECL/ECL Fanout Buffer ICS853S310I DATA SHEET General Description Features The ICS853S310I is a low skew, high performance 1-to-8 Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL

Contextual Info: Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM VCCI VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VCCO ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VEE VTN TERMINATION LE INPUT HYS

ADCMP580

Abstract: ADCMP581 ADCMP582 MO-220-VEED-2 PRBS31 ADCMP582BCP-R2 CP-16-3 VCCO11
Contextual Info: Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 FEATURES FUNCTIONAL BLOCK DIAGRAM VCCI VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VCCO ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VEE VTN TERMINATION LE INPUT HYS

maxim 872

Abstract: AN872 APP872 MAX9110 MAX9111 MAX9150 CML ECL termination
Contextual Info: Maxim > App Notes > BASESTATIONS / WIRELESS INFRASTRUCTURE INTERFACE CIRCUITS HIGH-SPEED INTERCONNECT Keywords: LVDS, low voltage, differential signaling signalling, lvds, EIA/TIA-644, high speed, clock distribution, ECL, PECL, CML, low noise emission, low power

TIA-644

Abstract: AN872 APP872 MAX9110 MAX9111 MAX9150
Contextual Info: Maxim > App Notes > Basestations/Wireless Infrastructure High-Speed Interconnect Interface Circuits Keywords: LVDS, low voltage, differential signaling, lvds, EIA/TIA-644, high speed, clock distribution, ECL, PECL, CML, low noise emission, low power Dec 13, 2001