MC100EPT23 Search Results

Contextual Info: MOTO RO LA °rderNumber:M R ro” Semiconductor Components M C 100EPT23 ♦ SO -8, D SUFFIX 8-LEAD PLASTIC SOIC PACKAGE CASE 751-06 ORDERING INFORMATION MC100EPT23D Product Preview D ual D iffe re n tia l LVPECL to LVTTL T ra n s la to r SOIC PIN DESCRIPTION

KPT23

Abstract: marking kpt23 MC100EPT23DG EPT23 MC100EPT23 AN1642
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package

KPT23

Contextual Info: MC100EPT23 Dual Differential LVPECL to LVTTL Translator The M C100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive EC L levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for

KPT23

Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate

KA23A

Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package

KPT23

Abstract: EPT23 MC100EPT23 MC100EPT23D power supply ps-02 diagram
Contextual Info: MC100EPT23 3.3VĄDual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate

Contextual Info: MC100EPT23 3.3VĄDual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate

EPT23

Abstract: KPT23 MC100EPT23 2x2 dfn
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT23

Abstract: EPT23 MC100EPT23
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT23

Abstract: EPT23 MC100EPT23 MC100EPT23D MC100EPT23DR2 MC100EPT23DT KA23
Contextual Info: MC100EPT23 3.3VĄDual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate

100EP

Abstract: EPT23 MC100EPT23 MC100EPT23D
Contextual Info: MOTOROLA Order Number: MC100EPT23/D Rev. 0.1, 05/1999 Semiconductor Components MC100EPT23 SO–8, D SUFFIX 8–LEAD PLASTIC SOIC PACKAGE CASE 751 ORDERING INFORMATION MC100EPT23D SOIC Product Preview Dual Differential LVPECL PIN DESCRIPTION to LVTTL Translator

Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate

Contextual Info: MOTO RO LA °rderNum berR “„c:°” Semiconductor Components M C100EPT23 ♦ SO -8, D SUFFIX 8-LEAD PLASTIC SOIC PACKAGE CASE 751 ORDERING INFORMATION MC100EPT23D SOIC Product Preview Dual D ifferential LVPECL to LVTTL Translator PIN DESCRIPTION • 2.0ns Typical Propagation Delay

EPT23

Abstract: KPT23 MC100EPT23 MC100EPT23D MC100EPT23DR2 MC100EPT23DT
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Dual D ifferential LVPECL to TTL Translator The MC100EPT23 is a dual differential LVPECL Because LVPECL Positive ECL levels are used only are required. The small outline 8-lead SOIC package design of the EPT23 makes it ideal for applications

Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT23

Abstract: EPT23 MC100EPT23 VDFN-8 mc100ept23dg
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

KPT23

Abstract: marking kpt23 EPT23 MC100EPT23 MC100EPT23D MC100EPT23DR2 MC100EPT23DT
Contextual Info: MC100EPT23 3.3VĄDual Differential LVPECL to LVTTL Translator The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate

Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package

EPT23

Abstract: KPT23 MC100EPT23 MC100EPT23DG
Contextual Info: MC100EPT23 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The MC100EPT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL Positive ECL or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package

TTL 74-series IC LIST

Abstract: 74 Series Logic ICs TTL 74-series IC PO74G74 PO74G04 list cmos ics 49fct32805 49FCT3807 Potato Semiconductor 49FCT3805
Contextual Info: 04/18/07 Pin to Pin & Package to Package Compatible IC List Standard 1.65V -3.6 V TTL / CMOS Clock Buffer PotatoSemi PO49FCT3802A 1GHz 1 to 5 PO49FCT3803B 700MHz 1 to 7 PO49FCT3804 800MHz 2X1 to 4 PO49FCT3805B 800MHz 2X1 to 5 PO49FCT3806 750MHz 2X1 to 5 PO49FCT3807B

motorola D213 user guide

Abstract: SEMICONDUCTOR J601 eeprom u505 AD9226 J306 J307 J406 sine wave inverter schematic and firmware CR502 vr301 potentiometer
Contextual Info: High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALB FEATURES FUNCTIONAL BLOCK DIAGRAM Buffer memory board for capturing digital data used with high speed ADC evaluation boards to simplify evaluation 32 kB FIFO depth at 133 MSPS upgradable Measures performance with ADC Analyzer

Contextual Info: SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator Check for Samples: SN65EPT23 FEATURES 1 • • • • • • • Dual 3.3 V Differential LVPECL/LVDS to LVTTL/LVCMOS Buffer Translator

ICS83023

Abstract: ICS83023AM MC100EPT23
Contextual Info: PRELIMINARY ICS83023 Integrated Circuit Systems, Inc. DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER GENERAL DESCRIPTION ,&6 HiPerClockS FEATURES • 2 LVCMOS / LVTTL outputs The ICS83023 is a dual, 1-to-1 Differentialto-LVCMOS Fanout Buffer and a member of