100EP Search Results

MC100EP90

Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Contextual Info: MC10EP90, 100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.

KEP05

Abstract: HEP05 MC100EP05 MC10EP05
Contextual Info: MC10EP05, 100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance

transistor k81

Abstract: SY100EP33VKG SY100EP33VZC SY100EP33VZCTR SY10EP33VKC SY10EP33VKCTR SY10EP33VZC SY10EP33VZCTR EP-33
Contextual Info: SY10EP33V/100EP33V 5V/3.3V, 4GHz, ÷4 PECL/LVPECL Divider Precision Edge General Description The SY10/100EP33V is an integrated ÷4 divider. The VBB pin, an internally-generated voltage supply, is ECL Pro available to this device only. For single-ended input

MC10EP016

Abstract: MC100EP016 MC10E016
Contextual Info: MC10EP016, 100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD

EP29

Abstract: MC100EP29 MC10EP29
Contextual Info: MC10EP29, 100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.

MC100EP35

Abstract: EL35 HP35 KP35 MC10EP35 code KP35
Contextual Info: MC10EP35, 100EP35 3.3V / 5V ECL JK Flip−Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and

HEP58

Abstract: MC100EP58 MC10EP58
Contextual Info: MC10EP58, 100EP58 3.3V / 5VĄECL 2:1 Multiplexer The MC10/100EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices. The 100 Series contains temperature compensation. • 310 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical

m 1305

Abstract: MC10EP116 MC10EP116FA MC10EP116FAR2 D23011
Contextual Info: MC10EP116 Hex Differential Line Receiver The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.

Contextual Info: MC10EP56, 100EP56 3.3V / 5V ECL Dual Differential 2:1 Multiplexer Description The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are

Contextual Info: MC10EP105, 100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

Contextual Info: MOTO RO LA °rderNumber:M R ro” Semiconductor Components M C 100EPT23 ♦ SO -8, D SUFFIX 8-LEAD PLASTIC SOIC PACKAGE CASE 751-06 ORDERING INFORMATION 100EPT23D Product Preview D ual D iffe re n tia l LVPECL to LVTTL T ra n s la to r SOIC PIN DESCRIPTION

mux 8 inputs cmos

Abstract: MUX CMOS 100EP SY89112U SY89850U SY89851U SY89852U SY89853U SY89854U SY89856U
Contextual Info: Your 100EP PECL Logic Parts are Now Obsolete! Buffer & MUX Family Eliminates Stubs with Internal Termination All this from Micrel. And the Competition. RIP ◆ Internal Termination—No Stubs ◆ Directly Interface to AC- or DC-coupled Signals ◆ 2.5V and 3.3V Operation

EP57

Abstract: MC100EP57 MC10EP57 100EP57
Contextual Info: MC10EP57, 100EP57 3.3V / 5V ECL 4:1 Differential Multiplexer Description The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open pulled LOW via the input pulldown resistors the device can also be used as a differential 2:1 multiplexer

EP105

Abstract: MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2 marking CODE D2B
Contextual Info: MC10EP105, 100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

E131

Abstract: MC100EP131 MC10EP131 QFN32 QFN32* socket
Contextual Info: MC10EP131, 100EP131 3.3V / 5V ECL Quad D Flip−Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.

MC100EP90

Abstract: MC10EP90
Contextual Info: MC10EP90, 100EP90 −3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.

EP105

Abstract: MC100EP105 MC10EP105
Contextual Info: MC10EP105, 100EP105 3.3V / 5V ECL Quad 2−Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

Contextual Info: MC10EP90, 100EP90 -3.3V / -5V Triple ECL Input to LVPECL/PECL Output Translator Description The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.

MC100EP142

Abstract: MC10EP142
Contextual Info: MC10EP142, 100EP142 3.3V / 5V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in

MC100EP139DTG

Abstract: MC100EP139 MC10EP139 3815 dc
Contextual Info: MC10EP139, 100EP139 3.3V / 5V ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: MOTO RO LA °rderNumber:M RceI°„” Semiconductor Components M C 100EPT26 SO -8, D SUFFIX 8-LEAD PLASTIC SOIC PACKAGE CASE 751 ORDERING INFORMATION j D . J - rJ î i i 100EPT26D i r } - v j A vÎ SOIC V ü / Product Preview 1:2 F an o u t D iffe re n tia l

Contextual Info: MOTO RO LA °rder,tar5Jïïïï55S Semiconductor Components M C 100EP90 S O -2 0 , DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 9 48E O RDERING INFORMATION r . j - rJ k V -.v/ M 100EP90DT / i vj/ a 4 • *V . Product Preview PIN DESCRIPTION Triple LVECL to LVPECL

MC10EP01

Contextual Info: MC10EP016, 100EP016 3.3V / 5VĄECL 8-Bit Synchronous Binary Up Counter The MC10/100EP016 is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD

Contextual Info: MC10EP57, 100EP57 3.3V / 5V ECL 4:1 Differential Multiplexer Description The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open pulled LOW via the input pulldown resistors the device can also be used as a differential 2:1 multiplexer