AS4C4M Search Results

AS4C4M4F0-50

Abstract: AS4C4M4F0-50JC AS4C4M4F0-50JI AS4C4M4F0-50TC AS4C4M4F1-50 AS4C4M4F1-60JI
Contextual Info: AS4C4M4F0 AS4C4M4F1 5V 4Mx4 CMOS DRAM Fast Page mode Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time

4C4M4EOQ-50JC

Abstract: 4C4M4EOQ-50TC 4C4M4EOQ-60JC 4C4M4EOQ-60TC AS4C4M4E1Q-50JC
Contextual Info: March 2001 AS4C4M4EOQ AS4C4M4E1Q 4M ✕ 4 CMOS QuadCAS DRAM EDO family Features • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption

AS4C4M16S-6TIN

Abstract: AS4C4M16S-7TCN AS4C4M16S
Contextual Info: AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM SDRAM Alliance Memory Table1. Key Specifications Features • • • • • • • • • • • • AS4C4M16S Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation

Contextual Info: AS4C4M4E1 May 2001 4Mx4 CMOS DRAM EDO family Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time

Contextual Info: AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM SDRAM Alliance Memory Table1. Key Specifications Features • • • • • • • • • • • • AS4C4M16S Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation

AS4C4M32S-6BIN

Abstract: AS4C4M32S
Contextual Info: AS4C4M32S Revision History AS4C4M32S- 90 Ball TFBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Added 166MHz option -6 clock cycle time Typing error page 1 – change to header of Key Specificatons from AS4C8M32S to AS4C4M32S Typing error Frequency in Ordering information

4C4M4FOQ-50JC

Abstract: 4C4M4FOQ-50TC 4C4M4FOQ-60JC TSOP300
Contextual Info: March 2001 AS4C4M4FOQ AS4C4M4F1Q 5V 4M X 4 CMOS QuadCAS DRAM fastpage mode Features • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption

AS4C4M4E1-60JC

Abstract: AS4C4M4E1-50JC AS4C4M4E1-50JI AS4C4M4E1-50TC AS4C4M4E1-50TI AS4C4M4E1-60JI AS4C4M4E1-60TC AS4C4M4E1-60TI
Contextual Info: AS4C4M4E1 May 2001 4Mx4 CMOS DRAM EDO family Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time

dram

Contextual Info: 16 Me g FPM DRAM Meg AS4C4M4 Austin Semiconductor, Inc. 4M x 4 CMOS DRAM PIN ASSIGNMENT Top View WITH FAST PAGE MODE, 5 VOLT 24 Pin TSOP (DG) AVAILABLE AS MILITARY SPECIFICATIONS • MIL-STD-883 FEATURES • Fast Page Mode Operation • CAS\-before-RAS\ Refresh Capability

AS4C4M16S

Contextual Info: AS4C4M16S Revision History AS4C4M16S- 54PIN 400 MIL PLASTIC TSOP II PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Removed 6TAN –– automotive temp page 1 and page 52 see separate datasheet for this option Added 6TCN – 166MHz clock – commercial temp

FPM DRAM

Abstract: "24 pin" DRAM cmos dram dram DC current definition
Contextual Info: 16 Me g FPM DRAM Meg AS4C4M4 Austin Semiconductor, Inc. 4M x 4 CMOS DRAM PIN ASSIGNMENT Top View WITH FAST PAGE MODE, 5 VOLT 24 Pin TSOP (DG) AVAILABLE AS MILITARY SPECIFICATIONS • MIL-STD-883 FEATURES • Fast Page Mode Operation • CAS\-before-RAS\ Refresh Capability

AS4C4M32

Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM Alliance Memory Confidential Features • • • • • • • • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture 1M word x 32-bit x 4-bank Programmable Mode - CAS Latency: 2, or 3

AS4C4M4F1-60JC

Abstract: AS4C4M4F1-50 AS4C4M4F1-50JC AS4C4M4F1-50JI AS4C4M4F1-50TC AS4C4M4F1-50TI AS4C4M4F1-60JI AS4C4M4F1-60TC
Contextual Info: AS4C4M4F1 May 2001 5V 4Mx4 CMOS DRAM Fast Page mode Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time

Contextual Info: Preliminary information •■ I l A S4C4M 4E0 AS4C4M4E1 A 4 M x 4 C M O S DRAM EDO family Features • Organization: 4,194,304 words x 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 5 0 / 6 0 ns access tim e - 2 5 / 3 0 ns colum n address access time

Contextual Info: $XJXVW  $6&0 4 Š 0 [  &026 4XDG&$6 '5$0 ('2 IDPLO\ HDWXUHV • Refresh - 2048 refresh cycles, 32 ms refresh interval for AS4C4M4E1Q - RAS-only and hidden refresh or CAS-before-RAS refresh TTL-compatible • 4 separate CAS pins allow for separate I/O operation

Contextual Info: AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM SDRAM Alliance Memory Confidential Table1. Key Specifications Features • • • • • • • • • • • • AS4C4M16S Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz

Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM Alliance Memory Confidential Features • • • • • • • • • • • Clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture 1M word x 32-bit x 4-bank Programmable Mode - CAS Latency: 2, or 3

Contextual Info: 16 Meg FPM DRAM AS4C4M4 4M x 4 CMOS DRAM PIN ASSIGNMENT Top View WITH FAST PAGE MODE, 5 VOLT 24 Pin TSOP (DG) AVAILABLE AS MILITARY SPECIFICATIONS • MIL-STD-883 FEATURES • Fast Page Mode Operation • CAS\-before-RAS\ Refresh Capability • RAS\-only and Hidden Refresh Capability

Contextual Info: Advance information •■ AS4C4M4F0 II 5V 4Mx4 CMOS DRAM fast page mode Features • Organization: 4 ,1 9 4 ,3 0 4 words X 4 bits • High speed • RAS-only or CAS-before-RAS refresh • TTL-compatible, three-state I/O • JEDEC standard package - 4 5 / 5 0 / 6 0 ns RAS access time

Contextual Info: AS4C4M4F1 May 2001 5V 4Mx4 CMOS DRAM Fast Page mode Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time

Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM Confidential Advanced (Rev. 2.0, Feb. /2013) Features •              Overview The 128Mb AS4C4M32S SDRAM is a highspeed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32

AS4C4M32S-7TCN

Abstract: AS4C4M32S
Contextual Info: AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM (Rev.3.0, May. /2014) Alliance Memory Confidential Features • • • • • • • • • • • Clock rate: 143/166 MHz Fully synchronous operation Internal pipelined architecture 1M word x 32-bit x 4-bank

Contextual Info: 16 Meg FPM DRAM AS4C4M4 4M x 4 CMOS DRAM PIN ASSIGNMENT Top View WITH FAST PAGE MODE, 5 VOLT 24 Pin TSOP (DG) AVAILABLE AS MILITARY SPECIFICATIONS • MIL-STD-883 FEATURES • Fast Page Mode Operation • CAS\-before-RAS\ Refresh Capability • RAS\-only and Hidden Refresh Capability

TD 346

Abstract: DH338
Contextual Info: Advance information •■ I l AS4C4M 4E0 AS4LC4M 4E0 A 5V/3V 4Mx4 CMOS DRAM EDO Features • Organization: 4,194,304 words x 4 bits • High speed • RAS-only or CAS-before-RAS refresh • TTL-compatible, three-state I/O • JEDEC standard package - 4 5 / 5 0 / 6 0 ns ■RXS access tim e