AS4C4M16S Search Results

AS4C4M16S-6TIN

Abstract: AS4C4M16S-7TCN AS4C4M16S
Contextual Info: AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM SDRAM Alliance Memory Table1. Key Specifications Features • • • • • • • • • • • • AS4C4M16S Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation

Contextual Info: AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM SDRAM Alliance Memory Table1. Key Specifications Features • • • • • • • • • • • • AS4C4M16S Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation

AS4C4M16S

Contextual Info: AS4C4M16S Revision History AS4C4M16S- 54PIN 400 MIL PLASTIC TSOP II PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Removed 6TAN –– automotive temp page 1 and page 52 see separate datasheet for this option Added 6TCN – 166MHz clock – commercial temp

Contextual Info: AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM SDRAM Alliance Memory Confidential Table1. Key Specifications Features • • • • • • • • • • • • AS4C4M16S Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz

AS4C4M16S

Abstract: as4c4m16s-6te
Contextual Info: AS4C4M16S 4M X 16 CMOS Synchronous Dynamic RAM Jan 2007 Rev.3.4 Description The AS4C4M16S are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 1,048,576 x 16 x 4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up

Contextual Info: AS4C4M16S FEBRUARY 2011 64Mb / 4M x 16 bit Synchronous DRAM SDRAM Alliance Memory Table1. Key Specifications Features • • • • • • • • • • • • AS4C4M16S Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation

AS4C4M16S

Contextual Info: AS4C4M16S 64M – 4M x 16 bit Synchronous DRAM (SDRAM) Confidential FBGA - Rev 2, May. /2014 Features Overview Fast access time from clock: 5.4 ns Fast clock rate: 166 MHz Fully synchronous operation Internal pipelined architecture 1M word x 16-bit x 4-bank