AND8003/D APPLICATION NOTE Search Results

JEDEC J-STD-020d.1

Abstract: JESD625-a AND8003 12MSB17722C JEDEC J-STD-033b.1 jedec JESD625-a AND8003/D APPLICATION note JESD625 J-STD-020d.1 JEDEC J-STD-020d
Contextual Info: AND8003/D Storage and Handling of Drypacked Surface Mounted Devices SMD Prepared by: R. Kampa, D. Hagen, W. Lindsay, and K.C. Brown Revised by J. Guzman−Guevarra http://onsemi.com APPLICATION NOTE INTRODUCTION The Humidity Indicator Card provides the customer with a

and8003

Abstract: A112 A113 resistance ALUMINUM
Contextual Info: AND8003/D Storage and Handling of Drypacked Surface Mounted Devices SMD http://onsemi.com Prepared by: R. Kampa, D. Hagen, W. Lindsay, and K.C. Brown APPLICATION NOTE INTRODUCTION The desiccant packed in each bag will keep the internal humidity level below 20% RH for at least one year, under

kvt22

Abstract: transistor BD 540 MC100EL35 MC100EP52 MC10EP31 MC100EP35 MC10EP01 MC100EP31 MC10EPT20
Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Low Voltage Positive ECL levels are used, only +3.3 V and ground are required. The small outline

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

HLT22

Abstract: klt22
Contextual Info: MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5 V and ground are required. The small outline 8-lead package and the low

KLT20

Abstract: HLT20 SO-8 HLT20 TSSOP-8 socket ic so8 socket
Contextual Info: MC10ELT20, MC100ELT20 5V TTL to Differential PECL Translator The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of

Contextual Info: MC100EL59 5V ECL Triple 2:1 Multiplexer The MC100EL59 is a triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random

KV58

Contextual Info: MC100LVEL58 3.3V ECL 2:1 Multiplexer The MC100LVEL58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and works from a 3.3 V supply. With AC performance similar to the EL58 device, the LVEL58 is ideal for low voltage applications which require the ultimate in AC

KVL01

Contextual Info: MC100LVEL01 3.3V ECL 4−Input OR/NOR The MC100LVEL01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in

transistor BD 2420

Abstract: MARKING QB
Contextual Info: MC100LVEL12 3.3V ECL Low Impedance Driver The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply.

Contextual Info: MC100LVEL59 3.3V ECL Triple 2:1 Multiplexer The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device

Contextual Info: NB3N3010B 3.3V, 12.288 MHz Audio Oversampling Clock Generator for USB Applications http://onsemi.com Description MARKING DIAGRAMS* 8 VDD 1 A L Y W M G 4 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package Note: Microdot may be in either location

marking 802 soic8

Abstract: NB3N3010BDR2G DFN8 2X2
Contextual Info: NB3N3010B 3.3V, 12.288 MHz Audio Oversampling Clock Generator for USB Applications http://onsemi.com Description MARKING DIAGRAMS* 8 VDD 1 A L Y W M G 4 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package Note: Microdot may be in either location

KPT22

Abstract: C100EPT22
Contextual Info: M C 100EP T22 Dual LVTTL/LVCMOS to D ifferen tial LVPECL T ran slator The M C100EPT22 is a dual LVTTL/LVCM OS to differential LVPECL translator. Because LVPECL Positive EC L levels are used only +3.3V and ground are required. The small outline 8-lead SOIC

AND8003

Abstract: MC10EPT20 AND8003/D APPLICATION note EPT20 HPT20 MC10EPT20D MC10EPT20DR2
Contextual Info: MC10EPT20 LVTTL/LVCMOS to Differential LVPECL Translator The MC10EPT20 is a LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3V and ground are required. The small outline 8–lead SOIC package and the single gate of the EPT20 makes it ideal for those

KPT22

Abstract: 100EP EPT22 MC100EPT22 MC100EPT22D MC100EPT22DR2 application note AND8003
Contextual Info: MC100EPT22 Dual LVTTL/LVCMOS to Differential LVPECL Translator The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3V and ground are required. The small outline 8–lead SOIC package and the single gate of the EPT22 makes it ideal for those

100EL90

Abstract: Application Note AND8002/D
Contextual Info: MC100EL90 −3.3V / −5V Triple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL

transistor BD 2420

Abstract: KVL31
Contextual Info: MC100LVEL31 3.3V ECL D Flip-Flop with Set and Reset The MC100LVEL31 is a D flip-flop with set and reset. The device is functionally equivalent to the EL31 device but operates from a 3.3 V supply. With propagation delays and output transition times essentially

qn04

Abstract: EP210S MC100EP210S MC100EP210SFA MC100EP210SFAR2 MARKING CODE QA1
Contextual Info: MC100EP210S 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver The MC100EP210S is a low skew 1−to−5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to

KPT21

Abstract: 100EP MC100EPT21 MC100EPT21D MC100EPT21DR2 EPT21
Contextual Info: MC100EPT21 Differential LVPECL to LVTTL Translator The MC100EPT21 is a Differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3V and ground are required. The small outline 8–lead SOIC package makes the EPT21 ideal for applications which require the translation of a

KPT23

Contextual Info: MC100EPT23 Dual Differential LVPECL to LVTTL Translator The M C100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive EC L levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for

KLT23

Contextual Info: MC100ELT23 5 V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used, only +5 V and ground are required. The small outline 8-lead package and the dual gate design of the ELT23 makes it ideal for applications which require the

KVL58

Abstract: MC100LVEL58 MC100LVEL58D MC100LVEL58DR2
Contextual Info: MC100LVEL58 2:1 Multiplexer The MC100LVEL58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and works from a –3.3V supply. With AC performance similar to the EL58 device, the LVEL58 is ideal for low voltage applications which require the ultimate in AC

Contextual Info: MC100LVEL30 3.3V ECL Triple D Flip−Flop with Set and Reset The MC100LVEL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the