AND8003 Search Results

and8003

Abstract: A112 A113 resistance ALUMINUM
Contextual Info: AND8003/D Storage and Handling of Drypacked Surface Mounted Devices SMD http://onsemi.com Prepared by: R. Kampa, D. Hagen, W. Lindsay, and K.C. Brown APPLICATION NOTE INTRODUCTION The desiccant packed in each bag will keep the internal humidity level below 20% RH for at least one year, under

JEDEC J-STD-020d.1

Abstract: JESD625-a AND8003 12MSB17722C JEDEC J-STD-033b.1 jedec JESD625-a AND8003/D APPLICATION note JESD625 J-STD-020d.1 JEDEC J-STD-020d
Contextual Info: AND8003/D Storage and Handling of Drypacked Surface Mounted Devices SMD Prepared by: R. Kampa, D. Hagen, W. Lindsay, and K.C. Brown Revised by J. Guzman−Guevarra http://onsemi.com APPLICATION NOTE INTRODUCTION The Humidity Indicator Card provides the customer with a

NB6N11SMNG

Contextual Info: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

Contextual Info: NB3N106K 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The NB3N106K is a differential 1:6 Clock fanout buffer with High−speed Current Steering Logic HCSL outputs optimized for ultra low propagation delay variation. The NB3N106K is designed

5621 transistor

Abstract: 4gd1
Contextual Info: NB6L295 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs Multi−Level Inputs w/ Internal Termination The NB6L295 is a Dual Channel Programmable Delay Chip http://onsemi.com designed primarily for Clock or Data de−skewing and timing

100EL91

Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
Contextual Info: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them

E212 transistor

Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

AND8020

Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
Contextual Info: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL

KPT25

Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Contextual Info: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

KVT23

Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
Contextual Info: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which

MC100EP90

Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Contextual Info: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.

MC100E116

Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
Contextual Info: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.

Contextual Info: NB3F8L3005C 3.3V / 2.5V / 1.8V / 1.5V 1:5 LVCMOS Fanout Buffer Description The NB3F8L3005C is a 2:1:5 Clock / Data fanout buffer operating on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V / 1.5 V VDDOx supplies which must be equal or less than VDD.

MC100LVEL01

Abstract: MC100LVEL01D 1085 SPICE model
Contextual Info: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in

Contextual Info: NCV7430 Automotive LIN RGB LED Driver The NCV7430 is a single−chip RGB driver intended for dedicated multicolor LED applications. The RGB LED driver contains a LIN interface slave for parametric programming of LED color and intensity. The device receives instructions through the LIN bus and

KEL04

Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
Contextual Info: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those

N100

Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

KEP05

Abstract: HEP05 MC100EP05 MC10EP05
Contextual Info: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance

NBXDBA012

Abstract: NBXDBA012LN1TAG on-semiconductor data
Contextual Info: NBXDBA012 3.3 V, 106.25 MHz / 212.5 MHz LVPECL Clock Oscillator The NBXDBA012 dual frequency crystal oscillator XO is designed to meet today's requirements for 3.3ĂV LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide selectable 106.25

EP809

Abstract: MC100EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G
Contextual Info: MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into

100EL91

Abstract: MC100EL91 MC100LVEL91
Contextual Info: MC100EL91 5 V Triple PECL Input to −5 V ECL Output Translator Description The MC100EL91 is a triple PECL input to ECL output translator. The device receives standard voltage differential PECL signals, determined by the VCC supply level, and translates them to differential

MC10EP016

Abstract: MC100EP016 MC10E016
Contextual Info: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD

KVL11

Abstract: KV11 LVEL11 MC100LVEL11
Contextual Info: MC100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times