ALLOCATE Search Results

Contextual Info: TO SH IBA TM P90C400/401 3.1.2 EXF Exchange Flag For TM P90C400, “E X F ” , which is inverted when the command “E X X ” is executed to tran sfer d ata between the m ain register and the au x iliary register, is allocated to the first bit of memory address FF8FH .

LF3312

Contextual Info: LF3312 Product Brief DEVICES INCORPORATED 12Mbit Frame Buffer / FIFO Providing designers with a single-chip approach to Sequential and Random Data Access FEATURES: Configurable 12,441,600-bit Memory - Allocate as Single/Dual Channels - Selectable Input/Output Word Widths

MSL260G

Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)

E4405B

Abstract: 8648c agilent signal generator jammer gsm 143FH jammer circuit TD-SCDMA 2010M MAX2306 MAX2308
Contextual Info: WIRELESS, RF, AND CABLE Mar 26, 2003 TD-SCDMA Reference Design V1.0 This application note presents Maxim's TD-SCDMA reference design V1.0. TDSCDMA is the Chinese Third Generation 3G standard. China's government has allocated 3 frequency bands: 1880~1920MHz, 2010~2025MHz, and 2300~2400MHz.

Contextual Info: OMB-SER-488-4 MADE IN USA 4-CHANNEL IEEE-488/Serial Converter SERIAL I/O ߜ Controls up to Four RS-232 or RS-422 Devices from One IEEE Controller ߜ Each Serial Port Individually Programmable ߜ Built-In 64K Data Buffer Dynamically Allocates Data Storage ߜ XON/XOFF or

AES-128

Abstract: IDT74FCT245 MIPS32 RC32300 RC32365 "ESP"
Contextual Info: RC32365 IDTTM InterpriseTM Integrated Communications Processor Device Overview – – – – – – – 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or

HMS M11

Abstract: ITT K12 series switch AES-128 IDT74FCT245 MIPS32 RC32 RC323 RC32300 RC32365 d13 -620 gh
Contextual Info: IDT T M InterpriseT M Integrated Communications Processor Device Overview – – – – – – – 2-way set associa tive LRU replacement algorithm 4 word lin e size Sub-block ordering Byte parity Per line cache lockin g Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or

AMD k86

Contextual Info: Implementation of Write Allocate in the K86 Processors Application Note Publication # 21326 Rev: D Issue Date: May 1998 Amendment/0 This document contains information on a product under development at Advanced Micro Devices AMD . The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Contextual Info: RC32365 IDTTM InterpriseTM Integrated Communications Processor Device Overview – – – – – – – 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or

0x00000010

Abstract: 0x300000C0 0x0000000b E 32.0000 C 000D 10B5 0x300000C4 0x10000000-0x2FFFFFFF
Contextual Info: PLX Technology PCI9060/68040 DEMO Memory Map 06/24/96 PCI Configuration Registers PCI CFG Offset BIT 0x00000000 0-15 0x00000002 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

0x00000564

Abstract: 0x00000404 0x00000532 0x0000047C 0x000005BE STI3400 0x0000040A sgs 8 r 15 93CS46 0x0000045C
Contextual Info: PLX Technology SGS PCI MPEG Board I/O MAP 07/15/96 PCI Configuration Registers PCI CFG Offset 0x00000000 0x00000002 BIT 0-15 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

PI3PCIE3412

Abstract: PI3PCIE3415 PCI Express 3.0 motherboard PCB diagram Lanes PI3PCIE34xx PCI Express display port connector pcie X8 connector PC MOTHERBOARD CIRCUIT diagram
Contextual Info: New Product Databrief PI3PCIE3412/PI3PCIE3415 PCI Express 3.0 Signal Switch Products Pericom’s PI3PCIE34xx PCI Express 3.0 Signal Switches provide a way to allocate PCI Express lanes and bandwidth by allowing the limited PCI Express lanes from the root complex to be dynamically

AN703

Abstract: DS80C400
Contextual Info: Application Note 703 Embedded Networking with IPv6 www.maxim-ic.com OVERVIEW Address space for Internet Protocol IP nodes is getting tight. Although not all of the 232 (roughly 4 billion) IPv4 addresses1 have been allocated yet (and in 2001 there was a slight dip in the previous

hc-05

Abstract: HC05 HC08 HC11 motorola hc11
Contextual Info: Release Notes SmartLinker RELEASE NOTES SmartLinker RELEASE NOTES SmartLinker V5.0.8 List of new Features • • HIWARE Format, _OVERLAP section, only used for ST7/HC05: New option –CallocUnusedOverlap: When this option is specified, this linker does allocate unreferenced variable in the overlap segment. Without this option, such

FE8D

Abstract: AN703 DS80C400 FE80 "routing tables"
Contextual Info: Application Note 703 Embedded Networking with IPv6 www.maxim-ic.com OVERVIEW Address space for Internet Protocol IP nodes is getting tight. Although not all of the 232 (roughly 4 billion) IPv4 addresses1 have been allocated yet (and in 2001 there was a slight dip in the previous

D12A

Abstract: D48A
Contextual Info: ® INNOVATION and EXCELLENCE Triple Output A-Series, TWR Models High-Reliability, Power-Sharing 20 Watt, DC/DC Converters A-SERIES Features • Low cost! Highly reliable! ■ Full 20 Watts output power ■ Power "user-allocated" among outputs ■ Proven SMT-on-pcb construction

AES-128

Abstract: IDT74FCT245 MIPS32 RC32300 RC32365 "ESP"
Contextual Info: RC32365 IDTTM InterpriseTM Integrated Communications Processor Device Overview – – – – – – – 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or

How COM Ports Are Allocated On Driver Installation

Abstract: AppNotes FT2232 pid vid advanced FT2232 pid vid FT2232H 0x6001 FT2232D ft4232 FT2232 FT4232H
Contextual Info: Future Technology Devices International Ltd. Application Note AN_123 How COM Ports Are Allocated On Driver Installation Document Reference No.: FT_000171 Version 1.0 Issue Date: 2009-08-27 The purpose of this application note is to clarify how COM ports are assigned when installing the FTDI

5b16

Abstract: C602 C607 HCS12 HCS12X 1803b0002101 186A0 00E0802F
Contextual Info: Technical Note TN 238 HCS12X – Data Definition The present document describes how programmer can help the HCS12X compiler to generate the more optimal code for data access. It will cover following topics: • Variables allocated in direct addressing area

Contextual Info: Extrusion Profiles Page 1 of 3 Back to search results 61030 This part is in stock! Inventory Snapshot: 176 feet* *Material in stock maybe allocated to other orders and is subject to prior sales Part Thermal Resistance Width Height Surface Area Weight Number °C/W at 3in length*

Contextual Info: QS75436 High-Speed CMOS 4K x 36 Block-Allocated Shared-Port RAM with Flexi-Burst Q FEATURES • Two independent 2K x 36-bit blocks • Independent port controls • Fast port access times: 20 ns, 25 ns, 30 ns - 50-MHz, 40-MHz, 33-MHz cycle times • Total bandwidth 3.6 Gbits/sec

AA0301

Abstract: SC11 DSP56302 SC10 SC12 D-6108 D2083
Contextual Info: SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56302 is available in a144-pin Thin

61219

Abstract: ACNH3112 12V 40A Relay ACNH3212
Contextual Info: CN-H ACNH3 HIGH LOAD RELAY FOR SMART J/B CN-H RELAYS (ACNH) FEATURES TYPICAL APPLICATIONS 1. Best space savings in its class. 2. Large capacity switching despite small size. Can replace micro ISO terminal type relays. 3. Terminals for PC board pattern designs are easily allocated.

Contextual Info: QS75436 ADVANCE INFORMATION High-Speed CMOS . . . . . . 4K x 36 Block-Allocated Shared-Port RAM with Flexi-Burst Q .„ QS75436 FEATURES • Two independent 2K x 36-bit blocks • Independent port controls • Fast port access times: 20 ns, 25 ns, 30 ns