RC32300 Search Results

MIPS32 instruction set

Abstract: t8kb 79RC32334 MIPS32 RC32300 RC5000 RC64474
Contextual Info: RISCore32300TM Family Integrated Processor Featur tures 79RC32334 Preliminary Information* ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – MIPS32 Instruction Set Architecture ISA – Cache prefetch instruction – Conditional move instruction

T4T15

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

T4T15

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – MIPS32 Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

79RC32332

Abstract: FCT245 RC32300 RC32332 RC32364 RC5000
Contextual Info: RISCoreTM 32300 Family Integrated Processor HDWXU WXUHV 79RC32332 ◆ ◆ RC32300 32-bit Microprocessor – Up to 133 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

332-DP

Contextual Info: RISCoreTM 32300 Family Integrated Processor HDWXU WXUHV 79RC32332 ◆ ◆ RC32300 32-bit Microprocessor – Up to 133 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

RC32364

Abstract: RC5000 79RC32332 FCT245 RC32300 RC32332 pfqp
Contextual Info: RISCoreTM 32300 Family Integrated Processor HDWXU WXUHV 79RC32332 ◆ ◆ RC32300 32-bit Microprocessor – Up to 133 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

AN-336

Abstract: RC32300
Contextual Info: 79RC32334/RC32332 Interrupt Modus Operandi RC32334/RC32332 Application Note AN-336 By Harold Gomard Notes Revision History Histor y November 5, 2001: Initial publication. Interrupt Scheme The Expansion Interrupt Controller extends the RC32300 CPU Core CP0 interrupt control by collating

79RC32334

Abstract: AN-361 IDT79RC32332 IDT79RC32334 RC32300 RC32332
Contextual Info: Booting from the Serial EEPROM for the First Time in Satellite Mode RC32334/RC32332 Application Note AN-361 By Fred Santilo Notes Revision History February 11, 2002: Initial publication. Background The RC32334/RC32332 are integrated processors based on the RC32300 CPU core. They incorporate

RC32300

Abstract: RC32364 R3052 R3081 R4640 R4650 MIPS Translation Lookaside Buffer TLB R3000 bta 137 HR08 bta 8 600
Contextual Info: RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300 RC32364TM Advance Information Integrated Device Technology, Inc. Features • High-performance embedded RISControllerTM microprocessor, based on IDT RC32300TM 32-bit CPU core - Based on MIPS-II RISC architecture with enhancements

Contextual Info: RISCoreTM 32300 Family Integrated Processor HDWXU WXUHV 79RC32332 ◆ ◆ RC32300 32-bit Microprocessor – Up to 133 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

RC32300

Contextual Info: RISController Embedded 32-bit Microprocessor, based on RISCore32300 Features • • High-performance embedded RISController™ micro­ processor, based on IDT RC32300™ 32-bit CPU core - Based on MIPS-II RISC architecture with enhance­ ments - Scalar 5-stage pipeline minimizes branch and load

RC32300

Abstract: RC32364 RC5000
Contextual Info: 3URGXFW %ULHI 5& ,QWHJUDWHG &RUH &RQWUROOHU HDWXUHV /LVW • • • RC32300 32-bit Microprocessor Up to 150 MHz operation Enhanced MIPS-32 ISA Cache prefetch instruction Conditional move instruction DSP Instructions Non-blocking load capability to speed IO processing

332-DP

Contextual Info: RISCoreTM 32300 Family Integrated Processor HDWXU WXUHV 79RC32332 ◆ ◆ RC32300 32-bit Microprocessor – Up to 133 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

power amplifier ic ta2040

Abstract: Nokia 6100 LCD TA2040 Transceiver Broadcom 3G RF interfacing 8051 with bluetooth modem Tripath TA2040 AMPLIFIER pixelworks L7205 tft interface with 8051 trw radar ac
Contextual Info: SEMICONDUCTOR TIMES JULY 2000 / 1 JULY 2000 FOCUSED ON EMERGING SEMICONDUCTOR COMPANIES Radar Scope Bay Microsystems Bay Microsystems was recently founded to develop chips. What kind? The company wouldn’t disclose any details to us. One rumor is “high-speed interfaces” whatever

Contextual Info:
    
   
        ! ! "# # Version 1.0 March 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A.

ejtag

Abstract: 79RC32334 FCT245 MIPS32 RC32300 RC32364 RC5000 IDT79RC32V334
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

RC32300

Abstract: RC32355 79RC32355 CRC-10 CRC-32
Contextual Info: 79RC32355 IDTTM InterpriseTM Integrated Communications Processor Features List SDRAM Controller – 2 memory banks, non-interleaved, 512 MB total – 32-bit wide data path – Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips – SODIMM support – Stays on page between transfers

BFC00380

Abstract: MTC0 RC32300 RC32332 RC32351 RC32355 RC32365 0xB800
Contextual Info: Reducing Power Consumption in the RC323xx Series Application Note AN-290 By Upendra Kulkarni Notes Revision History February 7, 2002: Initial publication. October 18, 2002: Changed device designation to RC3233x which includes 3 devices: RC32334, RC32333, and RC32332.

RC32300

Abstract: tiB-61 IDT RC32334 Users Manual PIO-12 MIPS32 RC32 RC32332 RC32364 TN-47
Contextual Info: Technical Note TN-47 Compatibility Between RC32334/ RC32332 and RC32364/RC32134 Based Solutions 1RWHV By Ian Ferguson ,QWU ,QWURGXFWLRQ Integrated Device Technology has developed a series of RISC processors to target embedded communications applications. All implement the MIPS Instruction Set Architecture ISA . One of these devices, the

IDT79RC4640

Abstract: RC3041 RC4640 RC4650
Contextual Info: IDT79RC4640 Low-Cost Embedded 64-bit RISController w/ DSP Capability HDWXUHV ◆ ◆ High-performance embedded 64-bit microprocessor – 64-bit integer operations – 64-bit registers – Based on the MIPS RISC Architecture – 100MHz, 133MHz, 150MHz, 180MHz, 200MHz and 267MHz