ACT273 Search Results

Contextual Info: 74AC273, ACT273 Octal D-Type Flip-Flop Features General Description • Ideal buffer for microprocessor or memory The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273SC 74ACT273SJ AC273 ACT273
Contextual Info: Revised March 2005 74AC273 • ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input

ACT273

Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/ACT273 Octal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273SC 74ACT273SJ AC273 ACT273
Contextual Info: 74AC273, ACT273 Octal D-Type Flip-Flop Features General Description • Ideal buffer for microprocessor or memory The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master

74ACT273SC

Abstract: AC273 74AC273 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273MTC ACT273
Contextual Info: Revised October 1999 74AC273 • ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input

ACT273

Abstract: ac273 74AC
Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/ACT273 O ctal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has e ig h t edge-triggered D-type flip -flo p s w ith individual D in p u ts and Q outputs. The com m on buffered C lock CP and M aster Reset

act273

Contextual Info: Q273 National ÆM Semiconductor 74ACQ273 • 54ACTQ/74ACTQ273 Quiet Series Octal D Flip-Flop General Description The ’AC/'ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buff­ ered Clock CP and Master Reset (MR) input load and re­

ACT273

Abstract: AC273
Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/ACT273 Octal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has eight edge-triggered D-type flip-flops w ith individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (15ÎÏÏ) inputs load and reset (clear) all flip-flops

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273SC 74ACT273SJ AC273 ACT273
Contextual Info: Revised August 2000 74AC273 • ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input

Contextual Info: AVG Semiconductors_ DDiT Technical Data DV74AC273 ACT273 Octal D Flip-Flop The DV74AC273/ACT273 has eight edge-triggered D-type flipflops with individual D inputs and Q outputs. The common buff­ ered Clock and Master Reset inputs load and reset clear all

Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/ACT273 Octal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops

Contextual Info: A I R C H November 1988 I L D Revised October 1999 S E M I C O N D U C T O R TM 74AC273 • ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The

74ACTO

Contextual Info: Q273 EH National ÆÆ Semiconductor 54ACQ/74ACQ273 • 54ACTQ/74ACTQ273 Quiet Series Octal D Flip-Flop General Description The ’AC/'ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buff­ ered Clock CP and Master Reset (MR) input load and re­

specifications of transistor AC126

Abstract: hc132a hc138a specifications of AC126 HC74A TC7PGU04FU transistor AC126 hc273a -toshiba toshiba vhc32 TC4W53FU
Contextual Info: SEMICONDUCTOR GENERAL CATALOG General-Purpose Logic ICs CMOS Logic ICs Low-Voltage CMOS Logic ICs CMOS Logic ICs in Ultra-Small US Packages Dual-Supply Level Shifters CMOS Bus Switch ICs Application-Specific Logic One-Gate CMOS L-MOS 1 2009-8 SCE0004I CMOS Logic ICs (74AC, 74VHC, 74HC and Standard Series) Quick Reference

transistor AC126

Abstract: equivalent transistor ac125 AC393 AC126 74AC393 AC365 AC682 d flip flop p6nk60z ACT03
Contextual Info: HC Portfolio Comparison PART # AC00 ACT00 AC01 AC02 ACT02 AC03 ACT03 AC04 ACT04 ACU04 AC05 ACT05 AC07 AC08 ACT08 AC09 AC10 ACT10 AC11 ACT11 AC14 ACT14 AC20 ACT20 AC32 ACT32 AC74 ACT74 AC86 ACT86 AC107 AC109 ACT109 AC112 ACT112 AC123 AC125 ACT125 AC126 ACT126

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS249B CD54AC273, CD74AC273 ACT273, ACT273 Octal D Flip-Flop with Reset August 1998 - Revised July 2002 Features Description • Buffered Inputs The ’AC273 and ’ACT273 devices are octal D-type flip-flops

ACT273

Abstract: 74ACT273 74ACT273B 74ACT273M DIP-20
Contextual Info: ACT273  OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 190 MHz ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX)

sc1097

Abstract: sc10970 SC10980 sc1098 SC-1097 74ACT273 74ACT273B 74ACT273M ACT273 DIP-20
Contextual Info: SGS-THOMSON ACT273 M IM i[Li gïïlHΩiD(3S OCTAL D-TYPE FLIP FLOP W ITH CLEAR PRELIM IN ARY DATA . . . . . . HIGHSPEED: fMAX = 190 MHz ns (TYP.) at Vcc = 5V LOW POWER DISSIPATION: Icc = 8 |xA (MAX.) at T a = 25 °C COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V (MAX)

AC273

Abstract: ACT273 CD54AC273 CD54AC273F3A CD54ACT273 CD74AC273 CD74AC273E CD74ACT273 CD74ACT273E
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS249B CD54AC273, CD74AC273 ACT273, ACT273 Octal D Flip-Flop with Reset August 1998 - Revised July 2002 Features Description • Buffered Inputs The ’AC273 and ’ACT273 devices are octal D-type flip-flops

AC273

Abstract: ACT273 CD54AC273 CD54AC273F3A CD54ACT273 CD74AC273 CD74AC273E CD74ACT273 CD74ACT273E
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS249B CD54AC273, CD74AC273 ACT273, ACT273 Octal D Flip-Flop with Reset August 1998 - Revised July 2002 Features Description • Buffered Inputs The ’AC273 and ’ACT273 devices are octal D-type flip-flops

CD74AC648

Abstract: CD74ACT109E CD74ACT648 CD74AC7060E CD74ACT651 SSI 280 CD74AC191 CD74AC651
Contextual Info: Product Selectors Index to Devices 4 CMOS-Compatible Logic Plastic Pkg.t C h ipt CD74ACOOE/M CD54AC00H CD74AC02E/M CD54AC02H CD74AC04E/M CD54AC04H CD74AC05E/M CD54AC05H TTL-Compatible Logic Chip t Plastic Pkg.t CD74ACT00E/M CD54ACTOOH CD74ACT02E/M CD54ACT02H

ACT273

Abstract: 74ACTQ273 C1995
Contextual Info: 74ACQ273  54ACTQ 74ACTQ273 Quiet Series Octal D Flip-Flop General Description The ’AC ’ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously

Contextual Info: Advanced CM OS Logic Advanced CMOS Logic, ACL, is the next step forward in the evolution of CMOS logic. It matches bipolar FAST* in speed, performance and logic type output drive, but at CMOS power levels. Just as HC/HCT high-speed CMOS logic became an indus­

MC74AC273

Abstract: MC74AC373
Contextual Info: MC74AC273, ACT273 Octal D Flip−Flop The MC74AC273/ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously.