ACCESS EMBEDDED SRAM Search Results

80C51

Abstract: CS6208
Contextual Info: Century Semiconductor Inc. CS6208 General Purpose 8-Bit Microcontroller /w Embedded Internet Access GENERAL DESCRIPTION FEATURES The CS6208 embedded network microcontroller is specifically targeted at applications that require network access. It incorporates a high-speed 4-cycle/

CS6208

Abstract: 80C32
Contextual Info: CS6208 General Purpose 8-Bit Microcontroller /w Embedded Internet Access FEATURES The CS6208 is an integrated device specifically targeted at embedded control applications that require network access. It incorporates a high-speed 8032-compatible micro-controller core along with

vhdl code for multiplexer

Abstract: vhdl code for multiplexer 32 vhdl code for sdram controller vhdl code for 8 bit common bus vhdl code for memory controller
Contextual Info: SIEMENS DRM256 Test Controller Embedded DRAM requires a dedicated solution for testing, derived from common DRAM test methods and taking into account that it is combined with logic like CPU cores, SRAM, ROM, etc. The test controller supportethree ways to access and communicate with the embedded DRAM core:

A23n

Abstract: F610 F612 MC68377 F6C6
Contextual Info: SECTION 4 FASRAM This document describes the fast access standby random access memory FASRAM , an intermodule bus 3 (IMB3) module, designed to be the memory of a system in the modular embedded controller family of modular microcontrollers from Motorola. This

hardware AES 256 controller

Abstract: MCF5328 MCF532x I2C MCF5327 MCF5327CVM240 MCF5328CVM240 MCF5329 MCF5329CVM240 MCF5329DS MCF532X
Contextual Info: ColdFire Embedded Controllers Specification Sheet MCF532x MCF532x Applications > Point-of-sale terminals > Health care-related instrumentation and monitoring > Security/access control panels > Factory service and maintenance systems > Heating, ventilation and air conditioning

MCF5273

Abstract: MCF5372 MCF5372L MCF5372LCVM240 MCF5373 MCF5373L MCF5373LCVM240 PIN DIAGRAM OF RJ45 to usb 196-BALL
Contextual Info: ColdFire Embedded Controllers Specification Sheet MCF537x MCF537x Applications > Voice-over-Internet Protocol VoIP > Health care-related instrumentation and monitoring > Security/access control panels > Factory service and maintenance systems > Heating, ventilation and air conditioning

32 KB SRAM

Abstract: mcf5213lcvm80 MC13192 MCF5211CAE66 MCF5211LCVM80 MCF5212 MCF5213 COLDFIRE2UM MCF5213CAF80 MCF5212CAE66
Contextual Info: ColdFire Embedded Controllers Specification Sheet MCF5211, MCF5212 and MCF5213 MCF521x Applications >Medical Pumps and Monitors >Point-of-Sale Terminals >Lighting Control Nodes >Security/Access Control Panels >Wireless Control Nodes >Machine Controls >Factory Service and Maintenance Systems

MoSys

Abstract: CL018G tsmc 0.18um MoSys sram embedded BWEB M1T1HT18PZ32E C-l018 32K32 MoSys 1T sram
Contextual Info: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 32-Bit wide data buses

MCF5222X

Contextual Info: ColdFire Embedded Controllers Specification Sheet MCF5222x Family MCF5222x Applications > ZigBee Control Nodes > 4-channel, 16-bit or 8-channel, 8-bit PWM generator > Security/Access Control Panels > Two periodic interrupt timers PITs for alarm and countdown timing

ADSP-TS203S

Abstract: ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory

0251X

Abstract: ADSP-TS202S smd code AA5 ADSP-TS201 SDRAM ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

ADSP-TS203S

Abstract: ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory

smd 03 jb3

Abstract: l3bc
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

ADSP-TS201 SDRAM

Abstract: TigerSHARC DSP Instruction set specification ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

DP83815

Contextual Info: DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer MacPhyter DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems.

stk14c88-3nf35i

Contextual Info: STK14C88-3 256 Kbit 32K x 8 AutoStore nvSRAM Features Functional Description • 35 ns and 45 ns Access Times The Cypress STK14C88-3 is a 256 Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology

SAM3u

Abstract: sam3u4 BALL 6686 ARM Cortex M4 ATSAM3U4EA cortex a15 cpu BGA144 ISO7816 LQFP100 LQFP144
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

sam3u4

Abstract: SAM3U4E usb to SDIO ATSAM3U4EA-AU AT91SAM BGA144 ISO7816 LQFP100 LQFP144 BALL 6686
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

usb to SDIO

Abstract: ADC12B sam3u 3 track magnetic card reader schematics ATSAM3U1EA-AU 6430FS
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

AT91SAM3U

Abstract: SAM3u smd G2 smd code Hall mar 552 SAM3u1 smd code Hall element marking code E5 SMD ic smd 662 WDV 806
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

AT91SAM3U4

Abstract: at91sam3 1N1308 MAR 735 REGULATOR IC 7912 pin identify AT91SAM3U4E SAM3u1 AT91SAM3U 3961 G.E 0x20180
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

Contextual Info: Features • Core • • • • • • – ARM Cortex -M3 revision 2.0 running at up to 100 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – 1024 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane

MX98224

Abstract: MX98224EC 64KX64 93C46 RXD17 memory ic 93c46 REG34H
Contextual Info: PRELIMINARY MX98224EC 24-port Dual-Speed Ethernet Switch Controller FEATURES l l l l l l l l l Single chip 24-port 10/100M wire speed Ethernet switching controller with all memory embedded Integration of 24-port dual speed, full/half duplex capable Media Access Controllers MACs with RMII

PF 08112

Abstract: BR3100 ADSP-TS203S ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS203S KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array