PAL12L10 Search Results

2829

Contextual Info: PAL12L10 — 195 — Series 24 & g tprl K 11 1« X Vcc = MAX le t h t) it. input - STD A A2 A4 ns 100 mA 25 max 0 .2 5 mA H — max 8 mA L «- min 3.2 mA - M n. : Pin 24 GND : Pin 12 C max r, .ii! y- STD FC Vcc R2 B 40 max H -* L — max max Ya l : i i ii

12L10

Abstract: 16l6 14l8 Monolithic Memories pal18l4 islez 18L4 20C1 PAL12L10 PAL14L8 PAL16L6
Contextual Info: Small 24 Series 12L10, 14L8, 16L6, 18L4, 20L2, 20C1 Small 24 Series PAL12L10 PAL14L8 PAL16L6 PAL18L4 PAL20L2 PAL20C1 INPUTS OUTPUTS POLARITY T rd ns Ice <mA) 12 14 16 18 20 20 10 8 6 4 2 2 LOW LOW LOW LOW LOW LOW 40 40 40 40 40 40 100 100 100 100 100 100

Contextual Info: Combinatorial PALI 2L10 Series 12L10,14L8,16L6 18L4,20L2,20C1 Ordering information Features/ Benefits • Combinatorial architecture PAL12L10 C NS STD • Security use PROGRAMMABLE ARRAY LOGIC T - PROCESSING STD = Standard XXXX = Other ' PACKAGE NS = Plastic

Contextual Info: Small 24 Series 12L10, 14L8, 16L6, 18L4, 20L2, 20C1 Small 24 Series PAL12L10 PAL14L8 PAL16L6 PAL18L4 PAL20L2 PAL20C1 INPUTS O U T PU T S POLARITY TpD ns (mA) 12 14 16 18 20 20 10 8 6 4 2 2 LOW LOW LOW LOW LOW LOW 40 40 40 40 40 40 100 100 100 100 100 100

PAL12L10CNS

Abstract: pal12l10
Contextual Info: Combinatorial PALI 2L10 Series 12L10,14 L8 ,16L6 18L4, 20L2, 20C1 Features/B enefits Ordering Information • Combinatorial architecture PAL12L10 C NS STD • Security fuse PROGRAMMABLE T ARRAY LOGIC - PROCESSING STD = Standard XXXX = Other ARRAY INPUTS - PACKAGE

12L10

Abstract: 16L6 PAL12L10 16JL Monolithic Memories pal18l4 18L4 20C1 PAL14L8 PAL16L6 PAL18L4
Contextual Info: ADV MICRO P LA /P LE /A RRAY S TL D e | Q25752ti GGË7SG5 Q T -4 6-1 3-4 7 '' C o m b in a to r ia l 1 2 L 1 0 , 1 4 L 8 , 1 6 L 6 P A L 1 2 L 1 0 1 8 L 4 , S e r ie s 2 0 L 2 , Ordering Information Features/Benefits • Combinatorial architecture PAL12L10 C NS STD

20xv10

Abstract: 20L10 GAL20XV10 GAL20XV10B-10LJ GAL20XV10B-10LP PAL12L10
Contextual Info: GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs

8L14

Abstract: pal6l16acns PAL6L16A
Contextual Info: ADV M I C R O P L A / P L E / A R R A Y S 1t / Ï Ë J Q2S7Sat OüäVl'H 8 T-46-13-47&#39; Decoder Series 6L16A 8L14A Ordering Inform ation Features/B enefits • 14 to 16 output* PAL6L16A C NS STD • Efficient Implementation of decoder« PROGRAMMABLE ARRAY LOGIC

CB4CLE

Abstract: cb4re CB8CLED cb8cle CB4CLED X74-160 x4202 CB16CE sr4cled 2 bit magnitude comparator using 2 xor gates
Contextual Info: ON LIN E R LIBRARIES G UI DE T ABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1410 Copyright 1993-1995 Xilinx Inc. All Rights Reserved. Contents Chapter 1 Xilinx Unified Libraries Overview .

7486 XOR GATE

Abstract: circuit diagram of half adder using IC 7486 7486 2-input xor gate ic 7486 XOR GATE pin configuration IC 7486 pin configuration of 7486 IC vhdl code for vending machine pin DIAGRAM OF IC 7486 data sheet IC 7408 laf 0001
Contextual Info: Lattice Semiconductor Handbook 1994 Click on one of the following choices: • Table of Contents • How to Use This Handbook • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Handbook 1994 i Copyright © 1994 Lattice Semiconductor Corporation.

PLSI 1016-60LJ

Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density

GAL20XV10B-10LP

Abstract: 20L10 20XV10 GAL20XV10 GAL20XV10B-10LJ PAL12L10
Contextual Info: Specifications GAL20XV10 GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES I/CLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output

Device-List

Abstract: cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2
Contextual Info: Device List Adapter List Converter List for ALL-11 JUL. 2000 Introduction T he Device List lets you know exactly which devices the Universal Programmer currently supports. The Device List also lets you know which devices are supported directly by the standard DIP socket and which

Contextual Info: Lattice GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOG Y — 10 ns Maximum Propagation Delay — Fmax = 1 0 0 MHz — 7 ns Maxim um from Clock Input to Data Output

GAL16V8

Abstract: GAL16VP8 GAL18V10 GAL20RA10 GAL20V8 GAL20VP8 GAL20XV10 GAL22V10 GAL26CV12
Contextual Info: Introduction to GAL Device Architectures Base Products - Aimed at providing superior design alternatives to bipolar PLDs, these five architectures replace over 98% of all bipolar PAL devices. The GAL16V8 and GAL20V8 replace forty-two different PAL devices.

81c78

Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
Contextual Info: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M

CM3000

Abstract: 20XV10B
Contextual Info: Lattice G A L 2 0 X V 1 0 B High-Speed E2CMOS PLD Generic Array Logic FU N CTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax =100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Com patible 16 mA O utputs

MSM 6290

Abstract: msm 5562 27c256 intel 62c512 AP 2068 27C512 microchip 62256 57C256 27C512 SGS-THOMSON 27C512-150
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

DMPAL20X8

Abstract: DMPAL20L10 DMPAL20L2
Contextual Info: Programmable Array Logic Series 24 Data Sheets Programmable Logic C T l National Ææ Semiconductor General Description The PAL S e rie s 24 fam ily co m p lim e n ts the P A L S e rie s 20 fam ily by providing tw o ad dition al in pu ts and two ad ditional ou tp u ts, allo w ing m ore co m p le x fu n c tio n s in

Contextual Info: 6L16A 8L14A Decoder Series Ordering Information F eatures/ Benefits • 14 to 16 outputs PAL6L16A C NS STD • Efficient implementation of decoders PROGRAMMABLE ARRAY LOGIC • Security fuse zr T Z PROCESSING STD - Standard XXXX = Other ARRAY INPUTS NS = Plastic

atmel 93c66

Abstract: PH29EE010 2764 EEPROM 537RU10 sst ph29ee010 556RT7A 556RT5 intel 8755 eprom 2716 537RU17
Contextual Info: Универсал ьны й програм матор Sterh ST­011 Производст во: Россия. Цен а: 17500 руб. с НД С. ST­011 имеет всего одну универсальную DIP­42 панель для программирования

PAL12L10MJS

Abstract: PAL14L8MJS 5962-8680402lx PAL14L8mj Monolithic Memories pal18l4 PAL12L10MJ PAL14L PAL18L4MJS PAL14L8 PAL16L6
Contextual Info: DESC FORM 193 MAY 86 Powered by ICminer.com Electronic-Library Service CopyRight 2003 _ i 1. _ SCOPE 1.1 Scope. This drawing describes device requirements for class B microcircuits in accordance with

PAL14L8

Abstract: 20C1A PAL12L10 PINOUT PAL12L10 PAL20L2 programming specification PAL18L4 PAL14L 18L4A PAL16L6 PAL20C1
Contextual Info: 24-Pin Small PAL Family ym National áíá Semiconductor Programmable Array Logic PAL 24-Pin Small PAL Family General Description The 24-pin Small PAL family contains six popular PAL archi­ tectures. The devices in the Small PAL family draw only 100 mA maximum supply current as compared to 210 mA in

pal20s

Abstract: PAL14H4-2 HAL16L8 HAL20S10 HAL16L8A-2 HAL20L8A PAL16R4A-2
Contextual Info: PAL -Programmable Array Logic H AL-Hard Array Logic Features/ Benefits • Reduce* SSI/MSI chip count peeler than 5 to 1 • Save* apace with SKINNYDIP® packages In addition the PAL/HAL provides these options: • Variable Input/output pin ratio • Programmable three-state outputs