MC74ACT10 Search Results

MC74ACT10N

Abstract: MC74AC10 MC74AC10D MC74AC10DR2 MC74AC10DT MC74AC10N MC74ACT10 MC74ACT10D MC74ACT10DR2
Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

74AC

Abstract: MC74AC10 MC74ACT10
Contextual Info: MC74AC10 MC74ACT10 Triple 3ĆInput NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 N SUFFIX CASE 646-06 PLASTIC 1 2 3 4 5 6 7 GND D SUFFIX CASE 751A-03 PLASTIC MAXIMUM RATINGS*

948F

Abstract: MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N
Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.

AC10g

Abstract: "NAND Gate" 74AC MC74AC10 MC74AC10N MC74ACT10
Contextual Info: MC74AC10, MC74ACT10 Triple 3−Input NAND Gate Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs • Pb−Free Packages are Available http://onsemi.com PDIP−14 N SUFFIX CASE 646 VCC 14 13 12 11 10 9 8 14 1 SOIC−14 D SUFFIX CASE 751A

Contextual Info: M O TO R O LA MC74A C 109 MC74ACT109 D ual J K P o sitiv e Ed ge-Trig gered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of tw o high-speed completely Independent transition clocked JK flip-flops. The clocking operation is independent o f rise and

MC74AC10

Abstract: MC74AC10D MC74AC10DR2 MC74AC10DT MC74AC10N MC74ACT10 MC74ACT10D MC74ACT10DR2 MC74ACT10N
Contextual Info: MC74AC10, MC74ACT10 Triple 3−Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs w These devices are available in Pb−free package s . Specifications herein apply to both standard and Pb−free devices. Please see our website at

Contextual Info: M MOTOROLA MC74AC10 MC74ACT10 Product Preview T rip le 3 -In p u t N A N D G ate TRIPLE 3-INPUT NAND GATE • O u tp u ts Source/S ink 24 m A • 'ACT10 Has TTL C o m p a tib le Inputs N SUFFIX CASE 646*06 PLASTIC i D SUFFIX CASE 751A-02 PLASTIC DC CHARACTERISTICS

Contextual Info: MC74AC10 MC74ACT10 Triple 3ĆInput NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 13 12 11 10 9 1 2 3 4 5 6 8 TRIPLE 3-INPUT NAND GATE 7 GND Figure 1. Pinout: 14–Lead Packages Conductors Top View N SUFFIX CASE 646-06

AC10g

Abstract: Q1/AC10G
Contextual Info: MC74AC10, MC74ACT10 Triple 3−Input NAND Gate Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs • Pb−Free Packages are Available http://onsemi.com PDIP−14 N SUFFIX CASE 646 VCC 14 13 12 11 10 9 8 14 1 SOIC−14 D SUFFIX CASE 751A

Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.

MC74AC10

Abstract: MC74AC10D MC74AC10DR2 MC74AC10DT MC74AC10N MC74ACT10 MC74ACT10D MC74ACT10DR2 MC74ACT10N
Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

Contextual Info: MOTOROLA MC74AC109 MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109 74ACT109 consists o f tw o high-speed co m ple te ly independent tra n s itio n clocked JK flip -flo p s. The clocking ope ra tio n is independent o f rise and

Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform.

Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP−14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO−14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14−Lead Packages Conductors

948F

Abstract: MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N
Contextual Info: MC74AC109, MC74ACT109 Dual JK Positive Edge-Triggered Flip-Flop The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop refer to

Contextual Info: b3b?252 OQTHBOG Ô2b « M O m bbE D MOTOROLA SC LOGIC MOTOROLA MC74AC109 MC74ACT109 Dual JK Positive Edge-TViggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The M C 74A C 10 9 /7 4 A C T 109 consists of tw o high-speed co m ple te ly independent

Contextual Info: MC74AC109 MC74ACT109 Dual JK Positive EdgeĆTriggered FlipĆFlop The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop refer to

Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

74AC

Abstract: MC74AC109 MC74ACT109
Contextual Info: MC74AC109 MC74ACT109 Dual JK Positive EdgeĆTriggered FlipĆFlop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall

MICRON RESISTOR cb 0229

Abstract: 2N2369 transistor pulse generator
Contextual Info: MC74AC10, MC74ACT10 Triple 3-Input NAND Gate • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs VCC 14 http://onsemi.com 13 12 11 10 9 8 PDIP–14 N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 SO–14 D SUFFIX CASE 751A 14 GND 1 Figure 1. Pinout: 14–Lead Packages Conductors

MC68B21CP

Abstract: xcm916x1cth16 transistor marking code 12W SOT-23 sg379 MC68B54P XC68HC805P18CDW mc68b50cp MC2830 NE555N CHN NE555N
Contextual Info: SG379/D REV 7 Semiconductor Products Sector NORTH AMERICA SALES AND DISTRIBUTION PRICE LIST THIS BOOK IS IN COMPUTER SORT PRODUCT CLASSIFICATION – Please see General Information Section 1.3 EFFECTIVE DATE: JANUARY 10, 1998 General Information 1 Cross References

transistor AC126

Abstract: equivalent transistor ac125 AC393 AC126 74AC393 AC365 AC682 d flip flop p6nk60z ACT03
Contextual Info: HC Portfolio Comparison PART # AC00 ACT00 AC01 AC02 ACT02 AC03 ACT03 AC04 ACT04 ACU04 AC05 ACT05 AC07 AC08 ACT08 AC09 AC10 ACT10 AC11 ACT11 AC14 ACT14 AC20 ACT20 AC32 ACT32 AC74 ACT74 AC86 ACT86 AC107 AC109 ACT109 AC112 ACT112 AC123 AC125 ACT125 AC126 ACT126

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

transistor mosfet buv18a

Abstract: M143206EVK MMBF4856 lm358 IC 68hc05sc24 telephone line interface circuit bc517 MC68B54 XC68HC705P9 MPX100ap BUV18A
Contextual Info: Device Index and Subject Index In Brief . . . Page Device Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1–1 General Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2–1 Subject Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2–9