LH5P8129 Search Results

Contextual Info: LH5P8129 CMOS 1M 128K x 8 CS-Control Pseudo-Static RAM FEATURES DESCRIPTION • 131,072 x 8 bit organization The LH5P8129 is a 1M bit Pseudo-Static RAM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access times (MAX.): 60/80/100 ns

80N80

Abstract: ENS-60
Contextual Info: MEMORIES Pseudo Static RAMs ★ Under developm ent C apacity C onfiguration Model No. A ccess tim e ns 60 LH5P860 70 80 100 120 150 - 64k x 8 LH5PB64 512k Pseudo Static RAM 32kx 16 LH5P1632 LH5P8128 1M 126kx8 LH5P8129 Low voltage operation 4M ★LH5PV8512

Contextual Info: LH5P8129 FEATURES • 131,072 x 8 bit organization CMOS 1 M 128K x 8 CS-Control Pseudo-Static RAM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TO P V IE W • Access times (MAX.): 60/80/100 ns • Cycle times (MIN.): 100/130/160 ns A l6 A i4 • Single +5 V power supply

Contextual Info: PRELIMINARY LH5P8129 FEATURES DESCRIPTION • 131,072 • Access times MAX. : 60/80/100 ns • Cycle times (MIN.): 100/130/160 ns • x 8 bit organization Power consumption: Operating: 572/440/358 mW (MAX.) Standby: 275 (iW (MAX.) in self-refresh mode •

LH5P8129-80

Contextual Info: PRELIMINARY LH5P8129 FEATURES • 131,072 x 8 bit organization • Access times MAX. : 60/80/100 ns • Cycle times (MIN.): 100/130/160 ns • Power consumption: Operating: 572/440/358 mW (MAX.) Standby: 275 jxW (MAX.) in self-refresh mode • CS Control Type

1M STATIC RAM "32 PIN"

Abstract: transistor A16 32-PIN LH5P8129 LH5P8129-60 LH5P8129-80
Contextual Info: CMOS 1M 128K x 8 CS-Control Pseudo-Static RAM LH5P8129 FEATURES • 131,072 × 8 bit organization PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Access times (MAX.): 60/80/100 ns RFSH 1 32 • Cycle times (MIN.): 100/130/160 ns VCC A16 2 31 A15 • Single +5 V power supply

Contextual Info: PRELIMINARY LH5P8129 DESCRIPTION FEATURES • 131,072 • Access times MAX. : 60/80/100 ns • Cycle times (MIN.): 100/130/160 ns • CMOS 1M (128K X 8) CS-Control Pseudo-Static RAM x 8 bit organization Power consumption: Operating: 572/440/358 mW (MAX.)

Contextual Info: MEMORIES Pseudo Static RAMs w B it co n fig u ra tio n C apacity Model No. A cce ss tim e n s 60 - 256k x8 70 80 100 120 150 LH5P832 LH5P860 x8 LH5P864 512k LH5P1632 x 16 LH5P8128 1M Pseudo Static RAM x8 LH5P8129 x8 LH5PV8512 x 16 LH5PV16256 x 16 LH6P82

Contextual Info: LH5P8129 FEATURES • 131,072 x 8 bit organization CMOS 1 M 128K x 8 CS-Control Pseudo-Static RAM PIN CONNECTIONS 3 2 -P IN D IP 3 2 -P IN S O P T O P V IE W • Access tim es (MAX.): 60/80/100 ns f RFSH C • Cycle tim es (MIN.): 100/130/160 ns • Single +5 V power supply

658128

Abstract: KM658128 TC518128 HM658128ALP-12 HM658128ALFP-8 HM658128P-12 tc518128apl HM658128ADP-12 HM658128ALP-8 KM658128-10L
Contextual Info: - 152 IM P s e u d o A X m & ÄSieH ít £ ca TAAC ns TCAC max (ns) V S t a t i c * V 7 R A M (1 31 0 7 2 x 8 ) 3 2 PI N ft TOE max (ns) TOH min (ns) TOD max (ns) TWP (ns) TDS min (ns) 6 5 8 1 2 8 A TDH min (ns) TWD min (ns) TWR max (ns) V D D or V CC

LH64256BK70

Abstract: Lh64256bk-70
Contextual Info: MEMORIES ★Under development • Pseudo S tatic RAMs Gipäfifty rüm ^H M o n Modal No. worfexblta t LH5P832/D/N-10 256k Supply.currant AOOMtttM# Cyetotime operating/standby (na)MAX. (na) MIN. 100 160 (mA) MAX. Supply voltage M Control signal« 65/3 32k x 8

LH61664AK-50

Abstract: LH61665AK lh61665 LH5PV8512 16256S
Contextual Info: PSEUDO SRAM/DYNAMIC RAM • PSEUDO SRAMs ♦ Features • Random access memory with ease of use equivalent to SRAM. Supply current MAX. C apacity Bit C onfiguration 256k x 8 Model No. LH 5P 832/D /N -10/12 Access time ns MAX. Cycle time (ns) MIN. O perating

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

Cross Reference

Abstract: Pseudostatic RAM TC51832
Contextual Info: Pseudo-Static RAM Cross Reference PSEUDO-STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 32K 64K 128K X X X 8 8 8 128K x 8 w/CS 512K 2-50 X 8 SHARP MODEL LH5P832 LH5P864 LH5P8128 COMPETITIVE VENDOR COMPETITIVE MODEL ACCESS TIME PACKAGE OPTIONS Hitachi

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

Contextual Info: MEMORIES SST/^-SS*!WW9!»a«i;!!WWS«»i ★ C apacity C onfiguration M odel No. 32k x 8 Under development A cce ss tim e n s 60 70 80 100 120 150 5 832 -i LH P -j LH P -j LH P -j LH P -j LH P H LH P 5 860 64k x 8 5 864 512k 3 2 k x 16 5 8128 128k x 8 1M

256k x 4

Contextual Info: MEMORIES ★Under development Capacity Configuration Model No. Access time ns 60 256k 32k x 8 70 Package SK BO 100 120 150 DIP SOP TSOP DIP LH5P832 — 28 28 LH5P860 n 28 32 64k x 8 LH5P864 — 32 512k Pseudo static RAM 32k x 16 LH5P1632 I- — 40 40 LH5P8128