LH5P832 Search Results

LH64256BK70

Abstract: Lh64256bk-70
Contextual Info: MEMORIES ★Under development • Pseudo S tatic RAMs Gipäfifty rüm ^H M o n Modal No. worfexblta t LH5P832/D/N-10 256k Supply.currant AOOMtttM# Cyetotime operating/standby (na)MAX. (na) MIN. 100 160 (mA) MAX. Supply voltage M Control signal« 65/3 32k x 8

p832

Abstract: P832-1
Contextual Info: LH5P832 FEATURES • 32,768 x 8 bit organization • Access time: 100/120 ns MAX. • Cycle time: 160/190 ns (MIN.) • Power consumption: Operating: 357.5/303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal

Contextual Info: MEMORIES Pseudo Static RAMs w B it co n fig u ra tio n C apacity Model No. A cce ss tim e n s 60 - 256k x8 70 80 100 120 150 LH5P832 LH5P860 x8 LH5P864 512k LH5P1632 x 16 LH5P8128 1M Pseudo Static RAM x8 LH5P8129 x8 LH5PV8512 x 16 LH5PV16256 x 16 LH6P82

Cross Reference

Abstract: Pseudostatic RAM TC51832
Contextual Info: Pseudo-Static RAM Cross Reference PSEUDO-STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 32K 64K 128K X X X 8 8 8 128K x 8 w/CS 512K 2-50 X 8 SHARP MODEL LH5P832 LH5P864 LH5P8128 COMPETITIVE VENDOR COMPETITIVE MODEL ACCESS TIME PACKAGE OPTIONS Hitachi

Contextual Info: LH5P832 FEATURES • 32,768 x 8 bit organization • Access time: 100/120 ns MAX. • Cycle time: 160/190 ns (MIN.) • Power consumption: Operating: 357.5/303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal

LH5P832N-12

Abstract: lh5p832n LH5P832
Contextual Info: LH5P832 FEATURES • 32,768 x 8 bit organization • Access time: 100/120 ns MAX. • Cycle time: 160/190 ns (MIN.) • Power consumption: Operating: 357.5/303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal

lh5p832n

Contextual Info: LH5P832 FEATURES • 32,768 x 8 bit organization • Access tim e: 120 ns MAX. • Cycle time: 190 ns (MIN.) • Power consum ption: Operating: 303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal

LH5P832N12

Contextual Info: LH5P832 FEATURES • 32,768 x 8 bit organization • Access time: 100/120 ns MAX. • Cycle time: 160/190 ns (MIN.) • Power consumption: Operating: 357.5/303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal

Contextual Info: LH5P832 FEATURES • 32,768 • Access time: 120 ns MAX. • Cycle time: 190 ns (MIN.) • x 8 bit organization Power consumption: Operating: 303 mW Standby: 16.5 mW • TTL compatible I/O • 256 refresh cycle/4 ms • Auto refresh is executed by internal

256k x 4

Contextual Info: MEMORIES ★Under development Capacity Configuration Model No. Access time ns 60 256k 32k x 8 70 Package SK BO 100 120 150 DIP SOP TSOP DIP LH5P832 — 28 28 LH5P860 n 28 32 64k x 8 LH5P864 — 32 512k Pseudo static RAM 32k x 16 LH5P1632 I- — 40 40 LH5P8128

lh5p832n

Contextual Info: LH5P832 CM OS 256K 32K x 8 Pseudo-Static RAM FEATURES The LH5P832 PSRAM has the ability to fill the gap between DRAM and SRAM by offering low cost, low standby power, and a simple interface. • 32,768 x 8 bit organization • Access time: 100/120 ns (MAX.)

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

80N80

Abstract: ENS-60
Contextual Info: MEMORIES Pseudo Static RAMs ★ Under developm ent C apacity C onfiguration Model No. A ccess tim e ns 60 LH5P860 70 80 100 120 150 - 64k x 8 LH5PB64 512k Pseudo Static RAM 32kx 16 LH5P1632 LH5P8128 1M 126kx8 LH5P8129 Low voltage operation 4M ★LH5PV8512

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

65256

Abstract: UPD42832C-15 PD42832C-15L UPD42832C-12L HM65256AP HM65256BLP-12 HM65256BP-12 LH5P832-10 upd42832 HM65256BP-10
Contextual Info: - 138 - 2 5 6 K X M % tt TAAC £ CC max ns) TCAC (ns) Pseudo A TOE -/ -fTOD ^ S t a t i c / TWP max (ns) TOH lain (ns) max (ns) min (ns) RAM (3 2 7 6 8 x 8 ) Í# tt TDS •in 2 8 P I N À an TWO TWR (ns) min (ns) min (ns) max (ns) TDH V D D or V C C (V)

IR2E01

Abstract: LR4087 LZ8420M LZ9GG13 LI3160 IR2C36 LZ2423A SM8205 LZ9GG13M LR39901
Contextual Info: Index Model No. A R M 7 D C PU C o re B i-C M O S 1 28 4 0 ,4 2 C 62 IR 3 Y 1 2 A 50 LH1532 49 LH 531V 00 2.4 IR 2 E 2 8 62 IR 3 Y 1 4 50 LH1536 49 LH 532000B 3,4 IR 2 E 2 9 62 IR 3 Y 1 5 50 LH 1540A 49 L H 5 3 2 00 0 B -1 3,4 IR 2 E 3 0 62 IR 3 Y 1 6 50

Contextual Info: MEMORIES SST/^-SS*!WW9!»a«i;!!WWS«»i ★ C apacity C onfiguration M odel No. 32k x 8 Under development A cce ss tim e n s 60 70 80 100 120 150 5 832 -i LH P -j LH P -j LH P -j LH P -j LH P H LH P 5 860 64k x 8 5 864 512k 3 2 k x 16 5 8128 128k x 8 1M