LH5P860 Search Results

80N80

Abstract: ENS-60
Contextual Info: MEMORIES Pseudo Static RAMs ★ Under developm ent C apacity C onfiguration Model No. A ccess tim e ns 60 LH5P860 70 80 100 120 150 - 64k x 8 LH5PB64 512k Pseudo Static RAM 32kx 16 LH5P1632 LH5P8128 1M 126kx8 LH5P8129 Low voltage operation 4M ★LH5PV8512

Contextual Info: MEMORIES Pseudo Static RAMs w B it co n fig u ra tio n C apacity Model No. A cce ss tim e n s 60 - 256k x8 70 80 100 120 150 LH5P832 LH5P860 x8 LH5P864 512k LH5P1632 x 16 LH5P8128 1M Pseudo Static RAM x8 LH5P8129 x8 LH5PV8512 x 16 LH5PV16256 x 16 LH6P82

8602 gn

Contextual Info: LH5P860 CMOS 512K 64K x 8 Pseudo-Static RAM FEATURES DESCRIPTION • 65,536 x 8 bit organization The LH5P860 is a 512K-bit Pseudo-Static RAM or­ ganized as 65,536 x 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in oscillator, it is easy to refresh memories without an

64k Static RAM

Abstract: 32-PIN LH5P860 5P860-1
Contextual Info: LH5P860 CMOS 512K 64K x 8 Pseudo-Static RAM FEATURES DESCRIPTION • 65,536 × 8 bit organization • Cycle time: 140 ns (MIN.) The LH5P860 is a 512K-bit Pseudo-Static RAM organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in

256k x 4

Contextual Info: MEMORIES ★Under development Capacity Configuration Model No. Access time ns 60 256k 32k x 8 70 Package SK BO 100 120 150 DIP SOP TSOP DIP LH5P832 — 28 28 LH5P860 n 28 32 64k x 8 LH5P864 — 32 512k Pseudo static RAM 32k x 16 LH5P1632 I- — 40 40 LH5P8128

LH64256BK70

Abstract: Lh64256bk-70
Contextual Info: MEMORIES ★Under development • Pseudo S tatic RAMs Gipäfifty rüm ^H M o n Modal No. worfexblta t LH5P832/D/N-10 256k Supply.currant AOOMtttM# Cyetotime operating/standby (na)MAX. (na) MIN. 100 160 (mA) MAX. Supply voltage M Control signal« 65/3 32k x 8

LH61664AK-50

Abstract: LH61665AK lh61665 LH5PV8512 16256S
Contextual Info: PSEUDO SRAM/DYNAMIC RAM • PSEUDO SRAMs ♦ Features • Random access memory with ease of use equivalent to SRAM. Supply current MAX. C apacity Bit C onfiguration 256k x 8 Model No. LH 5P 832/D /N -10/12 Access time ns MAX. Cycle time (ns) MIN. O perating

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

Contextual Info: • L ■. .n o r i> o u CMOS 512K 64K x 8 Pseudo-Static RAM FEATURES DESCRIPTION • 65,536 x 8 bit oiganization The LH5F06O is a 512K-bit Pseudo-Static RAM or­ ganized as 65,536 x 8 bits. It is fabricated using sNicorv-gate CMOS process technology* With its built-in

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3C08N ir2c53 ir2c05 li3301 IR3Y08 IR2E02
Contextual Info: Index Model No. IR3T ARM710 ARM7DI ARM7DM ARM7TDMI ARM7TDMI-SPL ARM8 ARM810 CMOS CMOS CMOS CMOS F series G series J series K series ID22 series ID222XX ID223XX ID224XX ID226XX ID227XX ID229XX ID22DXX ID22FXX ID22HXX ID240 series ID240DXX ID240EXX ID240GXX

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

IR2E01

Abstract: LR4087 LZ8420M LZ9GG13 LI3160 IR2C36 LZ2423A SM8205 LZ9GG13M LR39901
Contextual Info: Index Model No. A R M 7 D C PU C o re B i-C M O S 1 28 4 0 ,4 2 C 62 IR 3 Y 1 2 A 50 LH1532 49 LH 531V 00 2.4 IR 2 E 2 8 62 IR 3 Y 1 4 50 LH1536 49 LH 532000B 3,4 IR 2 E 2 9 62 IR 3 Y 1 5 50 LH 1540A 49 L H 5 3 2 00 0 B -1 3,4 IR 2 E 3 0 62 IR 3 Y 1 6 50

Contextual Info: MEMORIES SST/^-SS*!WW9!»a«i;!!WWS«»i ★ C apacity C onfiguration M odel No. 32k x 8 Under development A cce ss tim e n s 60 70 80 100 120 150 5 832 -i LH P -j LH P -j LH P -j LH P -j LH P H LH P 5 860 64k x 8 5 864 512k 3 2 k x 16 5 8128 128k x 8 1M