LH51256 Search Results

Contextual Info: LH51256/ CMOS 256K 32K x 8 Static RAM FEATURES DESCRIPTION • 32,768 x 8 bit organization The LH51256 is a 256K bit static RAM organized as 32,768 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access times: 100/120 ns (MAX.)

Contextual Info: LH51256 CMOS 256K 32K x 8 Static RAM FEATURES DESCRIPTION • 32,768 x 8 bit organization The LH51256 is a 256K bit static RAM organized as 32,768 x 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology.

Contextual Info: SHARP CORP blE » LH51256L FEATURES Access times: 100/120 ns MAX. • Power consumption: Operating: 248 mW (MAX.) (Ta = -40 to 85°C, minimum cycle) Standby: 5.5 (MAX.) (Ta = 0 to 60°C) DESCRIPTION The LH51256L is a 256K bit static RAM organized as 32,768 x 8 bits which provides low-power standby

lh51256l

Contextual Info: LH51256L CMOS 256K 32K x 8 Static RAM FEATURES DESCRIPTION • 32,768 x 8 bit organization Tiie LH51256L is a 256K bit state RAM organized as 32,768 x 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology.

organizational structure samsung

Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
Contextual Info: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116

LH51256N10L

Abstract: N12L LH51256 LH51256N-10L
Contextual Info: LH51256L DESCRIPTION FEATURES • 32,768 x 8 bit organization • Access times: 100/120 ns MAX. • Power consumption: Operating: 248 mW (MAX.) (T a = -40 to 85°C, minimum cycle) (MAX.) (T a = 0 to 60°C) • • Fully-static operation TTL compatible I/O

LH51256N10L

Abstract: LH51256 LH51256N-10L DIP02
Contextual Info: LH51256 CMOS 256K 32K x 8 Static RAM FEATURES DESCRIPTION • 32,768 × 8 bit organization The LH51256 is a 256K bit static RAM organized as 32,768 × 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology.

818l

Contextual Info: LH51256L DESCRIPTION FEATURES • 32 ,768 x 8 bit organization • Access times: 100/120 ns M AX. • Operating: 248 m W (M AX.) (T a = -40 to 85°C , minimum cycle) (M AX.) (T a = 0 to 60°C ) • Fully static operation • TTL compatible I/O • The LH51256L is a 256K bit static RAM organized

LH51256

Abstract: LH51256N-10
Contextual Info: LH51256 T~Yé-'2L3-/ CMOS 256K 32K x 8 Static RAM FEATURES DESCRIPTION • 32,768 x 8 bit organization The LH51256 is a 256K bit static RAM organized as 32,768 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access times: 100/120 ns (MAX.)

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

CMOS256K

Abstract: lh51256l
Contextual Info: • 32,768 x 8 bit organization • Access times: 100/120 ns MAX. • Power consumption: Operating: 248 mW (MAX.) (T a = -40 to 85°C, minimum cycle) Standby: 5.5 nW (MAX.) (Ta = 0 to 60°C) • • Fully-static operation TTL compatible I/O • Three-state outputs

BNK-17

Contextual Info: MEMORIES ★Under development • S ta tic RA M s Process Capacity Configuration words X bits Modal No. 2k X 8 Full CMOS 64k 8k X 8 256k 32k X 8 64k 8k X 8 64k X 4 256k 32k X 8 64k X 8 CMOS periphery 100 40/0.001 5 ± 10% O to 70 100 40/0.001 5 ± 10% - 4 0 to 85

LH5160N

Abstract: LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Features Functional Description The IH 5911, LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

LH5911

Abstract: lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Functional Description Features The LH5911. LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

UM61256AK-15

Abstract: UM61256ak sram um61256ck-20 HY62256ALP10 XL93LC46AP w24m257 GVT7164D32Q-6 km62256blg-7 w24m257ak-15 UM61256
Contextual Info: ISSI CROSS REFERENCE GUIDE Integrated Silicon Solution, Inc. ISSI ® Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM DRAM EEPROM EPROM FLASH MICROCONTROLLER SERIAL FLASH JULY 1998 Integrated Silicon Solution, Inc. CP005-1E 7/1/98 1 ISSI CROSS REFERENCE GUIDE

lh5168

Contextual Info: MEMORIES Static RAMs ★ Under development P ro ce ss C a p a c ity C o n fig u ra tio n Model No. A c c e s s tim e n s 70 80 90 100 120 LH5116 2k X 8 16k LH51116H Operating temperature : - 40 to 8 5 t IUUU "O LH5116S Supply voltage : 3 V±10% LH5168 Full

5268A

Abstract: 28-SOP LH521002AK-2S 28SOP LH52256CVN
Contextual Info: MEMORIES S tatic RAMs Process Capacity Configuation words Xbits 2k 16k 8 X Access time Supply current ns) MAX. Cycle time Operating, Standby (ns) MIN. !mA) MAX. (mA) MAX. Model No. Supply Operating voltage temp. 0C) m i i LH 5116/NA/D-10 100 40 0.001 5 ± 10%

um61256ak-15

Abstract: w24m257ak-15 um61256 um61256ck-20 um61256ak-12 km62256blg-7 KM68257Bp-20 W24M257AK HY6264ALP-10 w24M257
Contextual Info: ISSI Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM/NVM Serial EEPROM EPROM FLASH Static RAM SEPTEMBER 1996 CROSS REFERENCE GUIDE E2PROM ATMEL ISSI MIL PACKAGE SYMBOL PC P SC G SC GR AT93C46-10PC AT93C46-10PC-2.7 AT93C46-10SC AT93C46-10SC-2.7

LH52256-12

Abstract: LH52256-70 2SC5072 LH52258-20 LC36256AL-10 LC36256ALL-12 LC36256ALL-70 LC36257P-10 LC36257P-12 LH52256L-90
Contextual Info: - I 26 - 25 6K X m * tt & CC TAAC max os) TCAC max (ns) CMOS A TOE max (ns) 7 f y TOH rain (ns) TOD max (ns) S t a t i c / # R AM ( 3 2 7 6 8 X m ft TWP min (.is) TDS min (ns) TDH rain (ns) TWD min (ns) TWR m.ix (ns) V D D or V C C (V) 8) 28PIN A m I DD

LHS168

Abstract: LH52252A LH52252
Contextual Info: V .J 1 íVt! Static RAMs ★Under development Process Capacity Model No. Configuration Access time ns 70 -I 16k 2k Package 90 100 120 LH5116 J— I. 24 24 24 LH5116H 3 -T 24 24 24 - Z ÏÏ-J 1 24 24 24 C E , C S c o n tro l Data retention current : 0.2 pAjMAXj j

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

Contextual Info: CMOS 256K 32K FEATURES • 32,768 x 8 bit organization • Access times: 100/120 ns (MAX. • Power consumption: Operating: 248 mW (MAX.) (T a = -40 to 85°C, minimum cycle) Standby: 5.5 (MAX.) (T a = 0 to 60°C) • Fully static operation • TTL compatible I/O

100 10L AD

Abstract: LH521007AK-25 LH5168ST LH5168SHN lh5168 LH521002AK20
Contextual Info: MEMORIES • S ta tic R A M s Process Capacity ★ U nderdevelopm ent Configuration words Xbits Model No. Access tim e Supply current (ns) MAX. Cycle time operating/standby ImA) MAX. (ns) MIN. Supply voltage (V) Operating temperature (1C) Package LH5116/NA/D-10