51256L Search Results

HM51256

Abstract: HM51256P 51256LP 51256c
Contextual Info: HM51256 Series-2 6 2 1 4 4 -w o r d x t -bit C M O S Dynam ic Random A ccess M em o ry •FEATURE • • • 262, 144 word x 1 bit DRAM Double layer Poly-Si/Policide Process, high performance CMOS Power supply voltage: 5V ± 10% • Access time Row access time: 8 5 /1 0 0 /1 2 0 /1 50ns

CMOS256K

Abstract: lh51256l
Contextual Info: • 32,768 x 8 bit organization • Access times: 100/120 ns MAX. • Power consumption: Operating: 248 mW (MAX.) (T a = -40 to 85°C, minimum cycle) Standby: 5.5 nW (MAX.) (Ta = 0 to 60°C) • • Fully-static operation TTL compatible I/O • Three-state outputs

Contextual Info: SHARP CORP blE » 51256L FEATURES Access times: 100/120 ns MAX. • Power consumption: Operating: 248 mW (MAX.) (Ta = -40 to 85°C, minimum cycle) Standby: 5.5 (MAX.) (Ta = 0 to 60°C) DESCRIPTION The 51256L is a 256K bit static RAM organized as 32,768 x 8 bits which provides low-power standby

lh51256l

Contextual Info: 51256L CMOS 256K 32K x 8 Static RAM FEATURES DESCRIPTION • 32,768 x 8 bit organization Tiie 51256L is a 256K bit state RAM organized as 32,768 x 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology.

HM51256

Abstract: HM51256-15 HM51256ZP-8 51256CP-10 HM51256-8 HM51256-12 51256CP-8 51256P-8 51256P-15 M5125
Contextual Info: HM51256 Series 2 6 2 1 4 4 -w o rd X 1 -bit CMOS Dynamic Random Access Memory H M 5 1 2 5 6 P Series •FEATURE • 2 6 2 , 144 w ord x 1 bit D R A M • Plastic 16 pin D IP & 18 pin PLCC • Double layer Poly-Si/Policide Process, high performance CMOS •

LH51256N10L

Abstract: N12L LH51256 LH51256N-10L
Contextual Info: 51256L DESCRIPTION FEATURES • 32,768 x 8 bit organization • Access times: 100/120 ns MAX. • Power consumption: Operating: 248 mW (MAX.) (T a = -40 to 85°C, minimum cycle) (MAX.) (T a = 0 to 60°C) • • Fully-static operation TTL compatible I/O

Contextual Info: HM51256 Series 2 6 2 1 4 4 -word x 1 -bit CMOS Dynamic Random Access Memory •FEATURE • 2 6 2 , 144 word x 1 bit D R A M • Double layer Poly-Si/Policide Process, high performance CMOS • Power supply voltage: 5 V ± 10% • Access tim e D P-16B Row access tim e: 8 5 /1 0 0 /1 2 0 /1 5 0 n s

818l

Contextual Info: 51256L DESCRIPTION FEATURES • 32 ,768 x 8 bit organization • Access times: 100/120 ns M AX. • Operating: 248 m W (M AX.) (T a = -40 to 85°C , minimum cycle) (M AX.) (T a = 0 to 60°C ) • Fully static operation • TTL compatible I/O • The 51256L is a 256K bit static RAM organized

Contextual Info: HBS61409L Series 262,144 x 9 bit Dynamic Random Access Memory Module The H B 561409L is a 256k x 9 dynamic R A M module, mounted 9 pieces of 256k-bit low power D R A M H M 5 1 2 5 6 L C P sealed in PLCC package. A n outline of H B 561409L is 30-pin single-in-line package having two types; Lead type (HB561409AL)

Contextual Info: CMOS 256K 32K FEATURES • 32,768 x 8 bit organization • Access times: 100/120 ns (MAX. • Power consumption: Operating: 248 mW (MAX.) (T a = -40 to 85°C, minimum cycle) Standby: 5.5 (MAX.) (T a = 0 to 60°C) • Fully static operation • TTL compatible I/O