EP910A Search Results

Contextual Info: m ft i m intpl ¡PLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Extensive Software and Programming Support via Intel and Third-Party Tools

EPLD

Abstract: EP910A SR flipflops EP310 EP910
Contextual Info: E P 910 E P L D Features □ □ □ □ □ □ □ □ General Description H igh-perform ance 24-m acroeell EPLD Com binatorial speeds with t?D = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 M H z Pin-, function-, and JEDEC-File-com patible with A ltera's EP910A and

npld910-25

Abstract: 85C090 P85C090 p85c090-25 PLD910-15 TN85C090-25 INTEL PLD910 npld intel PLD NPLD910-12
Contextual Info: INTEL CORP MEMORY/PL] / SbE J> m 4 A 2 b l 7 b 0 0 7 7 5 1 7 514 • I T L 2 ir r te l. P W io - 1 ^ - 0 ^ ¡PLD910/85C090 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 Extensive Software and Programming

910-A01

Contextual Info: EP910A EPLD High-Performance 24-Macrocell Device March 1993, ver. 2 Data Sheet Supplement Features □ □ P relim inary Inform ation □ □ □ □ □ □ Highest-performance 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz

intel PLD

Abstract: INTEL PLD910 PLD910-25
Contextual Info: in tj ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpD 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 /¿A Typ. in

85C090

Contextual Info: IPKIlLOBilDKIÄKV i n y 85C090-12 24-M ACRO CELL CH M O S jliPLD Function, Pin, and JEDEC Compatible with 5C090, EP900, EP910 and EP910A Extensive Software and Programming Support via Intel and Third-Party Tools tpo 12 ns, 83.3 MHz w/Feedback, Clock to Output 8 ns

Contextual Info: EP910A EPLD Features Preliminary Information □ □ □ □ □ □ Highest-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns - Counter frequencies up to 100 MHz - Pipelined data rates up to 125 MHz Fabricated on advanced 0.8-micron CMOS EEPROM technology

85C090

Abstract: N85C090-15 P85C090 P85c090-25 D85C090-25 N85C090-25 P85C090-15 PLD910 TN85C090-25 ipld910
Contextual Info: inU . ¡PLD910/85C090 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • t PD 12 ns, 62.5 M H z w /F e e d b a c k , C lock to O u tp u t 8 ns ■ E xte n s iv e S o ftw a re an d P ro g ram m in g

Contextual Info: Features tPD Altera's EP910A Erasable P rog ra m m a ble Logic D ev ice EPLD is a pincom patible version of the EP910 EPLD. It offers e nhanced p erfo rm ance and is available in 600-m il, 40-pin DIP and 44-pin J-lead chip carrier packages (see Figure 9). The E P910A E P L D contains 24 macrocells with

Contextual Info: EP910A EPLD Features □ □ □ □ General Description Altera's EP910A Erasable Programmable Logic Device EPLD is a pincompatible version of the EP910 EPLD. It offers enhanced performance and is available in 600-mil, 40-pin DIP and 44-pin J-lead chip carrier

EP910T

Abstract: altera EP910 EP910-T
Contextual Info: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910

XC3030-70PC84C

Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 EP330PC XC3042-70PC84C A1020A-PL84C
Contextual Info: ULCt Cross-Reference Matra MHS Cross reference list of devices supported for ULC conversion is not exhaustiv as new devices are added regularly. Additional devices not shown in this list, may also be supported. MHS encourages you to contact your local TEMIC sales representative

Device-List

Abstract: cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2
Contextual Info: Device List Adapter List Converter List for ALL-11 JUL. 2000 Introduction T he Device List lets you know exactly which devices the Universal Programmer currently supports. The Device List also lets you know which devices are supported directly by the standard DIP socket and which

Contextual Info: Features a General Description Altera's EP910T Erasable Programmable Logic Device EPLD is a lowcost, high-performance version of the EP910 device. This EPLD operates in a turbo mode that is optimized for high-speed applications. The Turbo Bit in the device is preset at the factory. The EP910T EPLD is available in OTP

TCA780

Abstract: TFK U 111 B TFK U 4614 B TFK S 186 P TFK U 217 B TFK BP w 41 n TFK BPW 41 N Tfk 880 TFK 148 TDSR 5150 G
Contextual Info: Industry Part Number 1N3245 1N3611GP 1N3612GP 1N3613GP 1N3614GP 1N3725 1N3957GP 1N4001GP 1N4002GP 1N4003GP 1N4004GP 1N4005GP 1N4006GP 1N4007GP 1N4245GP 1N4246GP 1N4247GP 1N4248GP 1N4249GP 1N4678.1N4717 1N4728A.1N4761A 1N4933GP 1N4934GP 1N4935GP 1N4936GP

EPM5192L

Abstract: EPM5128L EPM5192J 2-0068-06234 EPM5032L EP910J 821573-1
Contextual Info: Selecting Sockets for J-Lead Packages Application Brief 46 September 1991, ver. 4 Introduction EPLD s solve m any of the problem s designers face today. T h e y offer low cost, low power, high reliability, and most im portantly, high integration density. Altera offers w ind ow ed ceram ic and on e -tim e -p rog ra m m a b le

altera EP910

Abstract: EP910-T IEP910 altera eplds EP910EPLD
Contextual Info: t ALTERA 47E CORP D • 05*15372 00020TM - r Tfl? o - ■ c f ALT EP910 EPLDs High-Performance 24-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ General Description Altera's EP910 Erasable Programmable Logic Devices EPLDs can

PDN0518

Abstract: EPM7128STC100-15 EP610ILC-10 EP610IPC-10 EPM7160STC100-10 EPM7064SLC44-10 EPM7064SLC44-10F EPM7128STC100 EP20K100BC356-2X ALTERA EPM7128STC100-15
Contextual Info: Page 1 of 4 PRODUCT DISCONTINUANCE NOTIFICATION PDN0518 Change Description: Altera will be discontinuing the APEX II, APEX 20K, APEX 20KC, APEX 20KE, Classic™, FLEX 8000, MAX® 3000A, MAX 7000, MAX 7000B, and MAX 7000S ordering codes listed in Tables 1 through 10.

altera ep900

Abstract: ep900 24-MACROCELL
Contextual Info: EP900 EPLD 24-Macrocell Device June 1993, ver. 1 Data Sheet Supplement Features □ □ □ □ □ □ 24-macrocell Classic EPLD Combinatorial speeds with tPD = 50 ns Counter frequencies up to 20.0 MHz Pipelined data rates up to 23.8 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

EP910dm

Abstract: EP910PC-30 EP910DC-40 EP1810LC-35 EP1810LC-20 EP610PC-15 Programming EP610DI-30 EP910JI-35 EP610IDC25 EP610SC-15
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

ulc xc3030

Abstract: PQFP 176 Xilinx XC3090 altera EP300 EPM7128 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
Contextual Info: ULC Reference Guide This reference guide lists most devices available for conversion. This list is not exhaustive, as new devices are added regularly. Additional devices not shown in this list may also be supported. Updated versions are available on the TEMIC web site. Check with factory if

Contextual Info: / an ù riü r * à \ September 1991, ver. 3 Operating Requirements for EPLDs Data Sheet Introduction A ltera EPLDs co m b in e a u n iq u e a rc h ite c tu re w ith an a d v a n c e d C M O S E PROM proce ss that p r o v id e s ex c eptional p e r f o rm a n c e w ith low p o w er.

ep330

Abstract: vhdl code for 4 bit counter vhdl code for sr flipflop EP610 ORDERING EPLD 900
Contextual Info: Classic Programmable Logic Device Family Data Sheet August 1993, ver. 1 □ Features □ □ □ □ □ □ □ □ □ Complete EPLD fam ily with logic densities up to 1,800 available gates 900 usable gates . See Table 1. M ultiple 20-pin PAL and GAL replacem ent and integration

dpld910

Abstract: pld910 IPLD910-25 DPLD910-15 adf simu 5C090 tcl eprom intel PLD INTEL PLD910 adf compiler
Contextual Info: i n t j . ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP91QA, 85C090 and 5C090 m tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns • Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 ju.A Typ. in