EP910 Search Results

EP910T

Abstract: altera EP910 EP910-T
Contextual Info: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910

Contextual Info: m ft i m intpl ¡PLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Extensive Software and Programming Support via Intel and Third-Party Tools

EP910

Abstract: EP910-35 FLIPFLOP SCHEMATIC 10KHZ 74HC EP910-30 EP910-40 EP910A
Contextual Info: FEATURES GENERAL DESCRIPTION • High density over 900 gates replacem ent for T T L and 74HC. • Advanced C M O S E P R O M tech n olo gy allow s erasability and reprogramrnability. The Altera EP910 Erasable Program m able Logic Device may be used to implement over 900 equiva­

EPLD

Abstract: EP910A SR flipflops EP310 EP910
Contextual Info: E P 910 E P L D Features □ □ □ □ □ □ □ □ General Description H igh-perform ance 24-m acroeell EPLD Com binatorial speeds with t?D = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 M H z Pin-, function-, and JEDEC-File-com patible with A ltera's EP910A and

npld910-25

Abstract: 85C090 P85C090 p85c090-25 PLD910-15 TN85C090-25 INTEL PLD910 npld intel PLD NPLD910-12
Contextual Info: INTEL CORP MEMORY/PL] / SbE J> m 4 A 2 b l 7 b 0 0 7 7 5 1 7 514 • I T L 2 ir r te l. P W io - 1 ^ - 0 ^ ¡PLD910/85C090 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 Extensive Software and Programming

EP910

Abstract: altera EP910
Contextual Info: EP910 EPLD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

Contextual Info: Features a General Description Altera's EP910T Erasable Programmable Logic Device EPLD is a lowcost, high-performance version of the EP910 device. This EPLD operates in a turbo mode that is optimized for high-speed applications. The Turbo Bit in the device is preset at the factory. The EP910T EPLD is available in OTP

910-A01

Contextual Info: EP910A EPLD High-Performance 24-Macrocell Device March 1993, ver. 2 Data Sheet Supplement Features □ □ P relim inary Inform ation □ □ □ □ □ □ Highest-performance 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz

intel PLD

Abstract: INTEL PLD910 PLD910-25
Contextual Info: in tj ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpD 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 /¿A Typ. in

EP-912

Abstract: EP9100
Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nS Tap Total 5, 10, 15, 20 6, 12, 18, 24 7 ,1 4,2 1 ,2 8 8, 16,24,32 9, 18, 27,36 10,20, 30,40 12, 24, 36, 48 15,30, 45,60 EP9100 EP9101 EP9102 EP9103 EP9104 EP9105 EP9106

EP910PC-30

Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA

Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP1810 900 300 450 16 24 48 Maximum user I/O pins 22 38 64 tp D n s 10 12 20 100 76.9 50 f CNT A-DS-CLASSIC-03 EP910 &

altera EP910

Abstract: EP910-T IEP910 altera eplds EP910EPLD
Contextual Info: t ALTERA 47E CORP D • 05*15372 00020TM - r Tfl? o - ■ c f ALT EP910 EPLDs High-Performance 24-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ General Description Altera's EP910 Erasable Programmable Logic Devices EPLDs can

EP600 programming

Abstract: ple3-12a Altera EP1800 EPS448 PLE3-12 EP610 ORDERING ep1800 EP600 altera ep900 PLED448
Contextual Info: PLED/J/G P L 1 D /J/G PROGRAMMING ADAPTORS PLED/J/G FEATURES GENERAL DESCRIPTION • Programming adaptors for Altera EPS448, EP600/ EP610, EP900/EP910, EP1210, EPB1400 and EP1800/ EP1810 EPLDs. The Altera PLED/J/G 448, 600, 900, 1210, 1400 and 1800 are enhancement products allowing device pro­

altera ep900

Abstract: altera EP910 EP900 74HC EP910 30MHx
Contextual Info: 24-M A C R O C E LL EPLD EP900 FEATURES GENERAL DESCRIPTION • High density logic replacement for TTL and 74HC. • Functional and pin compatible with the Altera EP910. • High speed, tpd = 45 ns. • Asynchronous clocking of all registers or banked register operation from 2 synchronous clocks.

Contextual Info: SMD 28 Pin 5 Tap TTL Compatible Active Delay Lines J-Lead P/N Delays are ±5% or ±2 nSt Tap Total 5, 10, 15, 20 6 , 12, 18, 24 7 ,1 4 ,2 1 ,2 8 8 ,1 6 ,2 4 , 32 9, 18, 27, 36 10, 20, 30, 40 12, 24, 36, 48 15, 30, 45, 60 EP9100 EP9101 EP9102 EP9103 EP9104

85C090

Contextual Info: IPKIlLOBilDKIÄKV i n y 85C090-12 24-M ACRO CELL CH M O S jliPLD Function, Pin, and JEDEC Compatible with 5C090, EP900, EP910 and EP910A Extensive Software and Programming Support via Intel and Third-Party Tools tpo 12 ns, 83.3 MHz w/Feedback, Clock to Output 8 ns

910T

Contextual Info: EP910T EPLD Features □ □ □ □ General Description A lte ra 's E P 910T E rasable P ro g ra m m a b le L ogic D ev ice E P L D is a low cost, h ig h -p erfo rm a n ce version o f the E P 910 d ev ice. T h is E PL D o p erates in a tu rbo m o d e that is op tim ized for h ig h -sp eed ap p licatio n s. T h e T u rb o Bit

Contextual Info: EP910A EPLD Features Preliminary Information □ □ □ □ □ □ Highest-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns - Counter frequencies up to 100 MHz - Pipelined data rates up to 125 MHz Fabricated on advanced 0.8-micron CMOS EEPROM technology

FC SUFFIX altera

Contextual Info: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates

dpld910

Abstract: pld910 IPLD910-25 DPLD910-15 adf simu 5C090 tcl eprom intel PLD INTEL PLD910 adf compiler
Contextual Info: i n t j . ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP91QA, 85C090 and 5C090 m tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns • Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 ju.A Typ. in

EP910

Contextual Info: EP910 EPLDs / a n High-Performance 24-Macrocell Devices U Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ u □ General Description tPD A lte ra's EP910 Erasable Program m able Logic D evices E P L D s can im plement up to 900 equivalent gates of SSI and M SI logic. These E P L D s

NEC D2732D

Abstract: nt68f63 novatek nt68f63 d2716d NEC D2716D atc 93lc46 D2732D CIRCUIT NEC D2716D TMS87C510 16V8H-25
Contextual Info: Dataman-48 Version 4.30 <ALL> Device List ALi M6759 www.dataman.com M6759 *44 M6759 *44Q M8720 AS29LV800B *44PS AS29LV800B *48TS AS29LV800T *44PS Altera EP1210 EP220 EP312 EP330 EP900 EP910-T EPC1064 EPC1213 EPC1441 as 1213 EPM3064A *44 EPM5192 @84 EPM7032AEas7032 *44

EP910

Contextual Info: EP910 EPLDs 'A Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ □ □ □ High-density replacement for TTL and 74HC with up to 900 gates High-performance 24-macrocell EPLD with tPD = 25 ns and counter frequencies up to 40 MHz Zero-power operation 20 (iA standby