TAC01 Search Results

Contextual Info: m ft i m intpl ¡PLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Extensive Software and Programming Support via Intel and Third-Party Tools

Contextual Info: Ml intpl 6 1992 ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Extensive Software and Programming Support via Intel and Third Party Tools

84-PIN

Abstract: CY7C341B
Contextual Info: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

K12J

Abstract: 100-PIN CY7C346 CY7C346B f 7400
Contextual Info: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

10KHZ

Abstract: 20L10 20RA10 74ALS 74HC 74HCT EP512
Contextual Info: F & I— J ^V J a \ 12 MACROCELL EPLD FEATURES GENERAL DESCRIPTION H igh Perform ance lo g ic replacem ent for T T L and 74HC or 74HCT SSI and M SI logic. High Speed, tpd = 25ns, and 40M H z operating frequency. "Zero Pow er” 150 f/A Standby Current . Twelve M acrocells with configurable I/O archi­

74HC

Abstract: 7C344 CY7C344 CY7C344B LTAC01
Contextual Info: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

D85C060-25

Abstract: PLD610 85C060 P85C060-25 PLD610-25 P85C060-15 D85C060-10 intel 85C060 n85c060 pld610-15
Contextual Info: intel ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610, 85C060 and 5C060 PLDs • tpD 10 ns, 100 M H z C o u n te r F req u en cy w /ln te rn a l F e e d b a c k ■ E xte n s ive S o ftw a re an d P ro g ram m in g

TAC01

Contextual Info: CY7C343 CYPRESS SEMICONDUCTOR 64-Macrocell MAX EPLD F eatures F unctional D escription • 64 MAX macrocells in 4 LABs The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible

Contextual Info: fax id: 6102 CY7C343 CY7C343B 64-Macrocell MAX EPLD Functional Description Featu res • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array The CY7C343/CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin

84-PIN

Abstract: CY7C341 CY7C341B
Contextual Info: CY7C341B ir CYPRESS . Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

74HC

Abstract: 7C344 CY7C344 CY7C344B 20C02 DD131
Contextual Info: CY7C344 CY7C344B *0 CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

Contextual Info: fax id: 6104 CY7C346 CY7C346B W CYPRESS 128-Macrocell MAX EPLDs ture is 100% user configurable, allowing the devices to accom­ modate a variety of independent logic functions. Features • • • • 128 macrocells in 8 LABs 20 dedicated inputs, up to 64 bidirectional I/O pins

Contextual Info: K? PRELIMINARY ? Js CYPRESS SEMICONDUCTOR = 192-Macrocell MAX EPLD software or by the model shown in Features Logic Array Blocks • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • Programmable interconnect array • 384 expander product terms

CY7C343

Abstract: CY7C343B
Contextual Info: CY7C343 » T C Y PR ESS Features CY7C343B 64-Macrocell MAX EPLD Functional Description • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C343

7c344

Abstract: 74HC CY7C344 CY7C344B W1220
Contextual Info: CY7C344 CY7C344B y CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

qml-38535

Abstract: smd marking 5 nw 82
Contextual Info: REVISIONS DATE DESCRIPTION LTR APPROVED YR-MO-DA REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS PMIC N/A 18 19 21 21 27 10 PREPARED BY 11 12 13 14 DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 CHECKED BY Rajesh Pithadia Michael Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS,

Contextual Info: CYPRESS SEMICONDUCTOR 4bE D B 2 5 0 ^ 2 'T 't- l l y - I V 0007103 T I ICYP 0*7 CY7C342 CYPRESS ß r SEMICONDUCTOR • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC,

Contextual Info: CY7C343 CYPRESS SEMICONDUCTOR 64-Macrocell MAX EPLD Features F unctional D escription • 64 MAX macrocells in 4 LABs The CY 7C343 is a high-perform ance, high-densityerasahle program m able logic device, available in 44-pin PLCC and H LC C packages. • 8 dedicated inputs, 24 bidirectional