EP610T Search Results

FC SUFFIX altera

Contextual Info: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates

Contextual Info: EP610T EPLD □ Features □ □ □ Altera's EP610T Erasable Programmable Logic Device EPLD is a lowcost, high-performance version of the EP610 device. This EPLD operates in a turbo mode that is optimized for high-speed applications. The Turbo Bit in the device is preset at the factory. The EP610T EPLD is available in

FP6101

Contextual Info: EP610T EPLD Features □ □ □ □ □ □ General Description A lte ra's EP610T E ra sab le P ro g ram m ab le L o g ic D evice EPLD is a low cost, h igh -p erform an ce v ersio n o f the EP610 d evice. T h is E P LD o p e rate s in a tu rb o m o d e that is o p tim ize d for h igh -sp ee d ap p lic atio n s. T he T urbo

EP610 "pin compatible"

Abstract: altera ep610
Contextual Info: bflE D ALTERA CORP • GS^S37B G0033S4 b7fl » A L T EP610A E P LD □ Features □ □ □ Preliminary Information □ □ □ Highest-performance, 16-macrocell Classic EPLD Combinatorial speeds with t PD = 7.5 ns Counter frequencies up to 125 MHz Pipelined data rates up to 142.9 MHz

altera ep610

Contextual Info: □ Features _l □ □ Advance Information J □ □ tPD Altera's EP610A Erasable Programm able Logic Device E P L D is a high­ speed version of the EP610 E P L D . It offers enhanced performance and is available in reprogrammable plastic 24-pin, 300-mil D IP ; 24-pin SO IC ; and

Contextual Info: EP610A EPLD AN b r ^ n ^ \ High-Performance 16-Macrocell Device March 1993, ver. 2 Data Sheet Supplement □ Features □ □ □ P re lim in a ry Inform ation □ □ □ □ □ □ Highest-performance 16-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns

programming manual EPLD EPS448

Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Contextual Info: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,

16cudslr

Abstract: EP320I EPM7160 Transition vhdl code for lift controller EPM9560 ep330 INTEL 8-series NEC 9801 altera ep220 Silicon Laboratories
Contextual Info: M+2Book Page i Thursday, June 12, 1997 12:49 AM MAX+PLUS II Programmable Logic Development System Getting Started Altera Corporation 2610 Orchard Parkway San Jose, CA 95134-2020 408 894-7000 M+2TOC+ Page iii Monday, June 9, 1997 9:34 AM Contents Preface

ulc xc3030

Abstract: PQFP 176 Xilinx XC3090 altera EP300 EPM7128 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
Contextual Info: ULC Reference Guide This reference guide lists most devices available for conversion. This list is not exhaustive, as new devices are added regularly. Additional devices not shown in this list may also be supported. Updated versions are available on the TEMIC web site. Check with factory if

EP610

Abstract: ep600i EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I
Contextual Info: EP610 EPLD H igh-perform ance, 16-macrocell Classic EPLD Com binatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Program mable I /O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

EP610

Abstract: altera ep610 AX2022 537e EP610-15 EP6101-10 EP610I
Contextual Info: E P 610 E P L D Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

fp6102

Abstract: FP6101 EP610-30 equivalent EP610-30 FP610 EP610 TI EP610 SSI IC adder L-72 EP610-35
Contextual Info: EP610 EPLD J Features J J J J J General Description Programm able clock option for independent clocking of all registers Macrocells in d ivid u ally programmable as D, T, JK , or SR flip-flops, or for combinatorial operation Extensive third-party software and programm ing support

ep330

Abstract: CLASSIC EPLD FAMILY altera EP1810
Contextual Info: Operating Requirements for Altera Devices March 1995, ver. 6 Datasheet A ltera devices com bine unique program m able logic architectures w ith advanced C M O S processes to p rovid e exceptional perform ance and re lia b ility. To m aintain the highest possible perform ance and re lia b ility of

Contextual Info: EP610 EPLD □ Features □ □ □ □ □ General Description Altera's EP610 Erasable Programmable Logic Device EPLD can implement up to 600 equivalent gates of SSI and MSI logic functions. It is available in space-saving w indowed ceramic or OTP plastic 24-pin, 300-mil DIP and

EP630

Abstract: EP630-15 EP630-20 altera ep610 EP610A
Contextual Info: EP630 EPLD □ Features □ □ □ Altera's EP630 Erasable Programmable Logic Device EPLD is a fast, lowpow er version of the EP610 device. The EP630 EPLD can implement a 16-bit counter at up to 83 MHz and typically consumes 5 m A when operating at 1 MHz. The EP630 EPLD is available in OTP plastic 24-pin,

EP610

Abstract: MIL-STD-883-compliant TI EP610 EP610-15 PALCE610 altera ep610 ALTERA MAX 5000 programming EP610-20 EP610I
Contextual Info: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

P610T

Contextual Info: AN b rVa\ LI IJ LI □ J □ □ □ LI □ H igh-d en sity re placem ent for T T L and 74 H C with up to 600 gates H ig h -p e rfo rm an ce 16-m acrocell E P L D w ith tPD = 15 ns and counter frequencies up to 83 M H z Z ero -p o w e r operation 20 |iA standby

PLDS-MAX

Abstract: Altera Classic EPLDs Altera LP5 ALTERA MAX 5000 programming ALTERA MAX 5000 eps448 logicaps sam plus mpm5192 PLDS-ENCORE
Contextual Info: Index September 1991 A+PLUS design entry 301 design processing 303 EPLD programming 304 functional simulation 304 o verview 299 ABEL2MAX Converter 356 adapters sff P L E D /J /G /S /Q & P L M D /J /G /S /Q adapters ADP (see Altera Design Processor) AHDL (s«1 Altera Hardware Description Language)

altera EP300

Abstract: EPM7128 EPLD ep330 mpm5192 MPM512 MPM5128 alternative bipolar transistors book
Contextual Info: M M r M p , 0 9 ra m m r .lv Data Sheet September 1991, ver. 2 Introduction 0 £ Programm able Logic Devices also described as P A L s , P L A s, F P L A s, PLD s, E P L D s , E E P L D s , LC A s, and F P G A s combine the logistical advantages of standard, fixed integrated circuits with the architectural flexibility of custom

Altera LP5

Abstract: Altera EP1800 logicaps schematic capture EPM5016 EP1810 PLEj1810 PLDS-MAX ep330 EPS448D 02D-00209
Contextual Info: AN Ü □ !^ V a \ Product Selection Guide Data Sheet September 1991, ver. 2 In t r o d u c t io n P r°d u c t Selection G uid e summarizes the range of products available from Altera: U □ U Ü U U U General-purpose E P L D s Function-specific E P L D s

ices49

Abstract: Altera ep330 ep330 Altera Classic EPLDs
Contextual Info: AN b □ n ^ \ Contents September 1991 Section 2 Classic EPLDs Classic EPLDs: A High-Speed, Low-Power Integration S o lu tio n . 37 EP330 EPLD: H igh-Perform ance 8-M acrocell D e v ic e .39 EP910 EPLDs: H igh-Perform ance 24-M acrocell D ev ices.77

EP610

Abstract: AX2022 EP610-30 EP610-25 EP610-35 EP610-15 EP610-20
Contextual Info: □ Features □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 15 ns Counter frequencies up to 83 MHz Pipelined data rates up to 83 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs Pin-, function-, and programming file-compatible with Altera's

EP610 "pin compatible"

Abstract: altera ep610 1CC3
Contextual Info: Features Preliminary Information □ □ □ □ □ □ □ Highest-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 7.5 ns Counter frequencies up to 125 MHz Pipelined data rates up to 142.9 MHz Fabricated on advanced 0.8-micron CMOS EEPROM technology

Date Code Formats Altera EPF10K

Abstract: ep22v10 5962-9061102XA 5962-8854901xa 8686401LA 5962-8686401LA lift controller in vhdl ALTERA PART MARKING EPM7160 EPX780 transistor b2020
Contextual Info: Introduction Contents March 1995 Introduction The PLD Advantages of Altera