DS534 Search Results

CE5C

Abstract: CEA 243 A12C A14C ZZ1A18 6803 microprocessor pcetc
Contextual Info: DALLAS SEMICONDUCTOR CORP BTE D m 2 b l 4] i 3D Q0033t>E S 1 3 DAL 0S5340 n~'5Z-!>V 0.5 DS5340 V40 Softener Chip DJy.!LAS SEMICONDUCTOR FEATURES PIN DESCRIPTION • Provides softness for V40-based systems • Adapts to task-at-hand: -Converts up to 672K bytes of CMOS

8086 assembly language for serial port

Abstract: 8086 hex code IBM POWER3 processor
Contextual Info: DS5340FP DALLAS S E M IC O N D U C T O R FEATURES DS5340FP V40 Softener Chip PIN DESCRIPTION • Provides softness for V40-based systems • Adapts to task-at-hand: - Converts up to 672K bytes of CMOS SRAM into lithium-backed NV program/data storage - Serial bootstrap loading for in-system

Contextual Info: MT9043 T1/E1 System Synchronizer Advance Information Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12

AN4502

Abstract: AN4503 AN4505 GP2401ESM18 3,3 kw high frequency transistor module
Contextual Info: GP2401ESM18 GP2401ESM18 Hi-Reliability Single Switch Low VCE SAT IGBT Module Replaces February 2000 version, DS5345-1.0 FEATURES • Low VCE(SAT) ■ High Thermal Cycling Capability ■ Non Punch Through Silicon ■ Isolated MMC Base with AlN Substrates DS5345-2.4 January 2001

GR-1244-CORE

Abstract: GR1244-CORE MT9043 MT9043AN TR62411 CB3LV-5I-20
Contextual Info: MT9043 T1/E1 System Synchronizer Data Sheet Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces

pll fm demodulator

Abstract: schematic diagram SCPC dm565 C337 725 mtld DS5347 Single Chip zero IF L-band Tuner DVB Satellite LK-19 Tuner ts pinout viterbi algorithm
Contextual Info: MT312 Satellite Channel Decoder Design Manual Supersedes DS5347 Issue 1.2 November 2001 DM5651 Key Features • • • • • • • • • • • • • • • January 2002 Ordering Information MT312C/CG/GP1N Conforms to EBU specification for DVB-S and

fir compiler v5

Abstract: ds534 DSP48 SRL16 XIP162 matched filter matlab codes fir compiler xilinx digital FIR Filter using distributed arithmetic MATLAB code for halfband filter fir compiler v4
Contextual Info: FIR Compiler v3.2 DS534 October 10, 2007 Product Specification Features General Description • Highly parameterizable drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, The Xilinx LogiCORE™ IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters

Contextual Info: DS5340 PRODUCT PREVIEW DALLAS S EM IC O N D U C T O R DS5340 V40 Softener Chip FEATURES PIN DESCRIPTION • Provides softness for V40-based systems • Adapts to task-at-hand: -Converts up to 672K bytes of CMOS SRAM into lithium-backed NV program/data storage

TR62411

Abstract: TMS 3450 GR-1244-CORE GR1244-CORE MT9043 MT9043AN
Contextual Info: MT9043 T1/E1 System Synchronizer Advance Information Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12

Contextual Info: MT9043 T1/E1 System Synchronizer Data Sheet Features DS5343 ISSUE 4 April 2002 Ordering Information • • • • • • • • • • Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12

siemens master drive circuit diagram

Contextual Info: MT9043 T1/E1 System Synchronizer Preliminary Information Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12

fir compiler v5

Abstract: fir compiler xilinx XC6SLX150-2FGG484 Polyphase Filter Banks 90CLK fir compiler v4 digital FIR Filter VHDL code polyphase FIR filter interpolation matlaB simulink design FDATOOL verilog code for interpolation filter
Contextual Info: FIR Compiler v5.0 DS534 June 24, 2009 Product Specification Introduction Overview The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters utilizing either Multiply-Accumulate MAC or

8132

Abstract: passivation DS5003
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244–3292 214 450–0400 Date: July 11, 1994 To: Subject: PRODUCT CHANGE NOTICE – F42101 Description: DS500X/DS53XX Passivation Change The DS500X and DS53XX products (DS5001, DS5002, DS5003, DS5004, DS5311, DS5340) will undergo a change in passivation from the current single layer 10 KA Hotwall OXIDE passivation to a 10

Contextual Info: DS501ST DS501ST Rectifier Diode Replaces October 2000, version DS5344-2.0 DS5344-3.0 October 2001 FEATURES KEY PARAMETERS • Double Side Cooling VRRM 600V ■ High Surge Capability IF AV 940A IFSM 11000A APPLICATIONS ■ Rectification ■ Freewheel Diode

Contextual Info: MT9043 T1/E1 System Synchronizer Data Sheet Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces

Contextual Info: MT9043 T1/E1 System Synchronizer Data Sheet Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces

CB3LV5

Contextual Info: MT9043 T1/E1 System Synchronizer Data Sheet Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces

DS501ST

Abstract: DS501ST01 DS501ST02 DS501ST03 DS501ST04 DS501ST05 DS501ST06
Contextual Info: DS501ST DS501ST Rectifier Diode Replaces October 2000, version DS5344-2.0 DS5344-3.0 October 2001 FEATURES KEY PARAMETERS • Double Side Cooling VRRM 600V ■ High Surge Capability IF AV 940A IFSM 11000A APPLICATIONS ■ Rectification ■ Freewheel Diode

DS501ST

Abstract: DS501ST01 DS501ST02 DS501ST03 DS501ST04 DS501ST05 DS501ST06
Contextual Info: DS501ST DS501ST Rectifier Diode Replaces October 2000, version DS5344-2.0 DS5344-3.0 October 2001 FEATURES KEY PARAMETERS • Double Side Cooling VRRM 600V ■ High Surge Capability IF AV 940A IFSM 11000A APPLICATIONS ■ Rectification ■ Freewheel Diode

AN4502

Abstract: AN4503 AN4505 AN4506 GP400DDS12
Contextual Info: GP400DDS12 GP400DDS12 Powerline N-Channel Dual Switch IGBT Module DS5341-1.1 February 2000 The GP400DDS12 is a dual switch 1200V, robust n channel enhancement mode insulated gate bipolar transistor IGBT module. Designed for low power loss, the module is suitable for a variety of high voltage applications

Contextual Info: MT9043 T1/E1 System Synchronizer Data Sheet Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces

transmitter qpsk schematic diagram

Abstract: receiver qpsk schematic diagram C337 w 79 diseqc DiSEqC 1.0 / 1.1 DM565 C337 W 61 qpsk transmitter w1447 CT-102
Contextual Info: MT312 Satellite Channel Decoder Design Manual Supersedes DS5347 Issue 1.2 November 2001 DM5651 Key Features • • • • • • • • • • • • • • • January 2002 Ordering Information MT312C/CG/GP1N Conforms to EBU specification for DVB-S and

siemens master drive circuit diagram

Contextual Info: MT9043 T1/E1 System Synchronizer Preliminary Information Features • • • • • • • • • • DS5343 Supports AT&T TR62411 and Bellcore GR1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12

Contextual Info: DS5340 PRODUCT PREVIEW DALLAS DS5340 V40 Softener Chip s e m ic o n d u c to r FEATURES PIN DESCRIPTION o«-cg<n^Lrtipr«. • Provides softness for V40-based systems: <<<<<<<< LO.Q.Q.Q.(LCLQ. • Adapts to task-at-hand: - Converts up to 672K bytes of CMOS