488NS Search Results

MT90812AL1

Abstract: TGE-5 EB32
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Mar 2011 Features • • • • • • • • • • • • • • • • • • MT90812AP MT90812AL MT90812APR MT90812AP1 MT90812AL1 MT90812APR1 192 channel x 192 channel non-blocking switching

hfc-s

Abstract: VAC L5051-X014-80 L5051-X014-80 l5051-x014 l5051 vogt 543 vogt f6 vogt 1N4148 PCM30
Contextual Info: DATA SHEET HFC - S 2BDS0 ISDN HDLC FIFO controller with S/T interface Copyright 1994 - 1997 Cologne Chip Designs All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by

PCM30 CODEC AUDIO

Abstract: PCM64 PCM30 SA15
Contextual Info: Cologne Chip "3@3 +:77@ 752'B8B3= %1'3'B 752#B8B3='1#3#B 8B3=73;2585>R^]ca^[[Ta fXcW '#X]cTVaPcTSBCX]cTaUPRTb _aT[X\X]PahTSXcX^] 9d]T! Copyright 1994-2001 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the

v 12276

Abstract: KS8620 KS8620D KS8620N BCK 2501
Contextual Info: 1 Chip CODEC for Digital Answering phone KS8620 INTRODUCTION 16-DIP-300 The KS8620 consists of on-chip PCM encoders, decoders PCM CODECs and PCM line filter. This device provide all the functions required to interface a fullduplex voice telephone circuit, digital answering phone.

MEB90812

Abstract: WARBLE TONE GENERATORS intel 8247 circuit diagram of car central lock system conference system MT8952 MT8952B MT90812 MT90812AL MT90812AP
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Features • • • • • • • • • • • • • • • • • • 192 channel x 192 channel non-blocking switching 2 local bus streams @ 2Mb/s supports up to 64 channels In TDM mode, the expansion bus supports up

Contextual Info: XRT5897 Seven-Channel E1 Line Interface X^EXqR December 1998-2 FEATURES • Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps E1 Rates • Seven Independent CEPT Transceivers • Supports Differential Transformer Coupled Receivers and Transmitters

Contextual Info: ZN5683E/J PCM LINE INTERFACE CIRCUIT The ZN5683E/J is a PCM line interface circuit suitable for 2.048Mbit/s or 8.448Mbit/s PCM systems. It contains both transmit and receive channels in a single 18 pin dual in-line package. The incom ing bipolar PCM signal, which has been

siemens Logo 230 rc manual

Abstract: GR-1244-CORE MT9044 MT9044AL MT9044AP TR62411
Contextual Info: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features November 2003 • Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces

503 20 010 10 vogt

Abstract: L5026 PCM64 APC smart VT circuit diagram vogt 543 VOGT b4 503 20 010 50 vogt transformer s3 FAH 23. smd MST 718 ST5069 valor
Contextual Info: Cologne Chip "3@3 +:77@ 752B\X]X 8B3=!13B 8B3=73;2585>R^]ca^[[Ta fXcW BCX]cTaUPRT P]S X]cTVaPcTS585>b 9P]dPah! Copyright 1994-2001 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the

T175

Abstract: PM4341A PM7345 PE-65774 VL1935
Contextual Info: PM4341A T1XC DATA SHEET PMC-900602 ISSUE 7 T1 FRAMER/TRANSCEIVER PM4341A T1XC SINGLE DSX-1 TRANSCEIVER DEVICE DATA SHEET ISSUE 7: JUNE 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM4341A T1XC DATA SHEET PMC-900602

CD4046 tone decoder

Abstract: ST811 PLL CD4046 application CD4046 pll application note CD4046 vco rotary binary coder S3507 S35061 S-350-7
Contextual Info: MAM I S3506I/S35071/S3507AI Industrial Temperature — is t a n d a r d p r o d u c t s CMOS Single Chip ¡¿-Law/ A-Law Synchronous Combo Codecs With Filters Features February 1993 • Encoder has Dual-Speed Auto-Zero Loop for Fast Acquisition on Power-up

Contextual Info: Preliminary 2P E X 4R XR-T5894 Four-Channel E1 Line Interface 3.3V .the analog plus com pany •- -, X« June 1997-3 FEATURES Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps (E1) Rates Logical Inputs Accept either 3.3V or 5.0V Levels Low CMOS Process

MT9076

Abstract: 7ga6
Contextual Info: MT9076 T1/E1/J1 3.3V Single Chip Transceiver Preliminary Information Features • The MT9076 is a highly featured single chip solution for terminating T1/E1/J1 trunks. It contains a longhaul LIU, an advanced framer, a high performance PLL, and 3 HDLCs. In T1 mode, the MT9076 supports D4, ESF and

01AH-01BH

Abstract: TR-TSY-000312 9508 PE64952 001H 041H PM4314 7G74 M8313
Contextual Info: PM4314 QDSX DATA SHEET PMC-950857 ISSUE 5 QUAD T1/E1 LINE INTERFACE DEVICE PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE DATA SHEET ISSUE 5: JUNE 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM4314 QDSX DATA SHEET

S3507

Abstract: AMI AMERICAN encoder 74175 ST110 PCM encoder circuit ami
Contextual Info: MAMA. S3506I/S3507I/S3507AI Industrial Temperature a m e r ic a n m ic r o s y s t e m s in c . CMOS Single Chip pi-Law/A-Law Synchronous Combo Codecs With Filters Features • Encoder has Dual-Speed Auto-Zero Loop for Fast Acquisition on Power-up • Low Absolute Group Delay = 450/isec @ 1kHz

Contextual Info: Cologne Chip "3@3 +:77@ 752B?280 8B3=!13B 8B3=73;2585>R^]ca^[[Ta fXcW BCP]S?28X]cTaUPRT P]S DRWX_bd_^ac 9P]dPah! Copyright 1994-2001 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the

AUTOMATIC light dim dip CONTROLLER

Contextual Info: CMOS ST-BUS FAMILY MT9079 Advanced Controller for E1  Features • • • • • • • • • ISSUE 5 Meets applicable requirements of CCITT G.704, G.706, G.732, G.775, G.796, I.431 and ETSI ETS 300 011 HDB3, RZ, NRZ fibre interface and bipolar

RG703

Abstract: ch8c ch6b Motorola LSC microcontroller DS26528 DS26521 DS26522 DS26524 DS26524GN 1103h
Contextual Info: DS26524 Quad T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26524 is a single-chip 4-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

vogt S4

Contextual Info: 41D1C855D 863C@39 9C4>"24C 9C4>84<3696?S_^db_\\Ub gYdX CDQ^T@39Y^dUbVQSU Q^T ESXY`ce``_bd Copyright 1994-1999 Cologne Chip Designs GmbH All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice.

ana60

Abstract: AFM2 AFM8 hdlc INTEL 386EX TDA 1512 STLC5466 TQFP176 Motorola CMOS Dynamic RAM 1M x 1 1989
Contextual Info: STLC5466 64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 64 TX HDLCs with broadcasting capability and/ or CSMA/CR function with automatic restart in case of Tx frame abort

20EF TRANSFORMER

Abstract: TRANSFORMER 20EF 20F9 rexton AAIS mark csc 9102 D3318
Contextual Info: PRODUCT PREVIEW GENERAL DESCRIPTION The DS26519 is a single-chip 16-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines. The DS26518 is a 8-port SCT. The DS26514 is a 4-port

11290

Abstract: TLS14
Contextual Info: DS26528 Octal T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26528 is a single-chip 8-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

wandel goltermann RFZ

Abstract: wandel goltermann sna wandel goltermann sna-2 RFZ-1 tektronix 1240 logic analyzer wandel goltermann RFZ 12 return loss bridge 16 x E1 G.703 7154-R
Contextual Info: XR-T5894 Four-Channel E1 Line Interface 3.3V or 5.0V November 1997-2 FEATURES • Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps (E1) Rates • Four Independent CERT Transceivers • Supports Differential Transformer Coupled Receivers and Transmitters

wandel goltermann RFZ

Abstract: RFZ-1
Contextual Info: XRT5894 Four-Channel E1 Line Interface 3.3V or 5.0V May 1998-2 FEATURES □ Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps (E1) Rates □ Four Independent CEPT Transceivers □ Logical Inputs Accept either 3.3V or 5.0V Levels Ultra-Low Power Dissipation