CY7C1333 Search Results

CY7C1333

Contextual Info: CYPRESS _ CY7C1333 6~Kx3? Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin c o m p a tib le and fu n c tio n a lly eq u iv alen t to ZB T™ d evic e M T 55L 64 L 32F • S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w a it sta tes

Contextual Info: fax id: 1088 CY7C1333 ADVANCED INFORMATION 64Kx32 Flow-Through SRAM with NoBL Architecture Features Functional Description • S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w ait sta tes— D ata is tra n s ferred on ev e ry clock • In te rn ally se lf-tim e d o u tp u t b u ffe r co n tro l to elim in a te

20306

Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

Contextual Info: CY7C1333H PRELIMINARY 2-Mbit 64K x 32 Flow-Through SRAM with NoBL Architecture Features • Low standby power Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states. The CY7C1333H is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support

tas 5352

Abstract: 64KX32 CY7C1333
Contextual Info: CY7C1333 64Kx32 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32F • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock

64KX32

Abstract: CY7C1333
Contextual Info: fax id: 1088 PRELIMINARY CY7C1333 64Kx32 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32F • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock

20306

Contextual Info: CY7C1333F 2-Mb 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states.Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support

A101

Abstract: CY7C1333F CY7C1333F-100AC
Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

A101

Abstract: CY7C1333F CY7C1333F-100AC 20306
Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

Contextual Info: fax id: 1088 " C YPR BSS PRELIMINARY CY7C1333 64Kx32 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin c o m p a tib le and fu n c tio n a lly eq u iv alen t to ZB T™ d evice M T 55L 64 L 32F • S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w a it sta tes

64KX32

Abstract: CY7C1333
Contextual Info: 333 CY7C1333 64Kx32 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32F • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock

Contextual Info: CY7C1333F 2-Mbit 64K x 32 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 117-MHz bus operations with zero wait states. Data is transferred on every clock. The CY7C1333F is a 3.3V, 64K x 32 Synchronous

nobl sram

Abstract: 8361H CEL9200 CY7C1333 CY7C1334 JESD22
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97328 VERSION 1.2 November, 1999 64K x 32 SRAM with NoBL Architecture R42D Technology, Fab 4 CY7C1333 64K x 32 Flow-Through SRAM with NoBl Architecture CY7C1334 64K x 32 Pipelined SRAM with NoBl Architecture

Switching regulator, Pin 5, Clock

Contextual Info: CY7C1333H PRELIMINARY 2-Mbit 64K x 32 Flow-Through SRAM with NoBL Architecture Features • Low standby power Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states. The CY7C1333H is a 3.3V, 64K x 32 Synchronous Flow-through Burst SRAM designed specifically to support

Contextual Info: fax id: 1088 ^ T C Y P P g g « f PBEUMmmY CY7C1333 64Kx32 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin c o m p a tib le and fu n c tio n a lly eq u iv alen t to ZB T™ d evic e M T 55L 64 L 32F • S u p p o rts 6 6 -M H z bus o p e ra tio n s w ith zero w a it sta tes

64K X 4 CACHE SRAM

Abstract: SRAM read/write circuit 64KX32 CY7C1333 CY7C1334 CY7C1350 CY7C1351 CY7C1352 CY7C1353 nobl sram
Contextual Info: fax id: 1503 NoBL: The Fast SRAM Architecture Introduction What is a NoBL? Processors in high performance PCs, workstations, communication equipment, and network applications demand high speed memories. The type of memory required is determined by the system architecture, the application and the processor

CY7C1333

Abstract: CY7C1334 CY7C1350 CY7C1351 CY7C1352 CY7C1353 nobl sram memory bandwidth nobl
Contextual Info: NoBL SRAM Fact Sheet Product Overview Cypress’s family of No Bus Latency NoBL™ Synchronous SRAMs offers the memory bandwidth required for high-performance networking applications. Unlike standard synchronous SRAMs, the NoBL family is designed specifically to satisfy

C133-10

Abstract: C1336 C133-14 CY7C133 CY7C143 IDT7133 IDT7143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

64KX32

Abstract: CY7C1333 CY7C1334 CY7C1350 CY7C1351 CY7C1352 CY7C1353
Contextual Info: fax id: 1503 Back NoBL: The Fast SRAM Architecture Introduction What is a NoBL? Processors in high performance PCs, workstations, communication equipment, and network applications demand high speed memories. The type of memory required is determined by the system architecture, the application and the processor

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

CY7C1350

Abstract: IDT71V546
Contextual Info: NoBL , The ZBT™-Compatible Family! Packaging is a key place to begin the comparison analysis. All NoBL devices are offered in a 100-pin TQFP package. This is an industry JEDEC standard package used for most synchronous SRAMs. The ZBT family is also being offered in

CY7C133

Abstract: CY7C143 IDT7133 IDT7143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

7C13

Abstract: CY7C133 CY7C143 IDT7133 IDT7143 bit-slice C1335
Contextual Info: fax id: 5202 1CY 7C13 3 CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power

CY7C133

Abstract: CY7C143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns