CLOCK Search Results

TC9303AN

Abstract: 6LW6 TC9303 tc9304f LCD12 TC9319F TC9301AN TC9309F
Contextual Info: Digital Tuning System DTS (1) System IC-LSI System No. Controller PLL prescaler DTS-9 A3 Operating Voltage Crystal Oscittation TC9301AN TC9172AP 4.5-5.5V 7.2MHz TC9303AN TC9227P 4.5-5.5V 7.2MHz Major Functions Receiving Band Preset Memory * Station Clock

UC3901 application diagrams

Abstract: UC2901 T270pF UC1901 scf 4242 UC3901
Contextual Info: y U N IT R O D E UC1901 UC2901 UC3901 Isolated Feedback Generator • Low-Cost Alternative to Optical Couplers • Internal 1% Reference and Error Amplifier • Internal Carrier Oscillator Usable to 5mHz • Modulator Synchronizable to an External Clock •

Contextual Info: SN74F378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S D FS 030B - D2932, M ARCH 1987 - REVISED O CTO B ER 1993 Contains Six D-Type Flip-Flops With Single-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input

TMS4116

Abstract: TMS4132
Contextual Info: MOS LSI TMS 4132 JDL 32,768-BIT DYNAMIC RANDOM-ACCESS MEMORY NOVEMBER 1979 32,768 «AX SUPPLY 1 X 1 Organization 10% Tolerance on All Supplies • All Inputs Including Clocks TTL-Compatible

ic tl 741

Abstract: S47C256
Contextual Info: AD V A N C E INFORM ATION TM S47C256 32,768-W ORD BY 8-BIT R EAD -O N LY M EM O R Y NOVEM BER 1 9 8 5 3 2 ,7 6 8 X 8 Organization N PACKAGE TOP VIEW Fully Static (No Clocks. No Refresh) NC C 1 y j 2 Q : 27 : A12 C 2 A7 C 3 26 : All Inputs and Outputs TTL Compatible

i486

Contextual Info: SN74BCT2141 2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM D3613. A UG UST 1990 2-Way 8K x 18 Bit Architecture FN PACKAGE TOP VIEW Synchronous Read and Write Access at 50 MHz Clock Frequency Incorporates Burst Counter for Burst-Read (Read-Hit) Cycles or Burst-Write (Line-Fill)

Contextual Info: TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE S C T S 0 2 9 A -A U G U S T 1989 -R E V IS E D JULY 1996 • Combined ADC, DAC, and Filters • Extended Variable Frequency Operation - Master Clock Up to 4.096 MHz - Sample Rates Up to 16 kHz - Passband Up to 6 kHz

Contextual Info: TLD369 DUAL CCD IMAGE SENSOR CLOCK DRIVER D 3 2 9 6 . JUNE 198 9 Dual Inverting MOS Driver P PACKAGE TOP VIEW Low Standby Power Dissipation NC Versatile Interface Circuit for Use between TTL Levels and Level-Shifted High-Current, High-Voltage Systems 1A

TM4SN64EPN10

Abstract: TM2SN64EPN-10 TM48N64EPN TM4SN64EPN-10 TMS626812
Contextual Info: TM2SN64EPN 2097152 BY 64-BIT TM4SN64EPN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES _ SYNCHRONOUS CLOCK CYCLE TIME *CK3 , {CL = 3 t ACCESS TIME CLOCK TO OUTPUT >CK2 CL = 2) *CK3 (CL = 3) *CK2 (CL = 2) • • • • • • • •

T5CD

Contextual Info: U M C U M 2661 Enhanced Programmable Communications Interface EPCI Features • Automatic serial echo mode (échoplex) ■ Local or remote maintenance loop back mode Baudrate: de to IM bps (1X clock) - de to 62.5K bps (16X clock) - de to 15.625K bps (64X clock)

Contextual Info: S E M I C O N D U C T O R , AND NETWORKING Section 2 - Data Sheets Data Sheets COMPUTING I N C GA1000 Custom Clock Generator. 2-3 GA1085 11-Output Configurable Clock B uffe r. 2-19

Contextual Info: SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR S D A S 2 1 8 A -A P R IL 1982 - REVISED DECEMBER 1994 SN54ALS273 . . . J PACKAGE SN74ALS273. . . DW OR N PACKAGE TOP VIEW Contain Eight Flip-Flops With Single-Rail Outputs Buffered Clock and Direct-Clear inputs

Contextual Info: o bq4850Y U N I T R O D E - RTC Module with 512Kx8 NVSRAM Features General Description >• I n te g r a t e d SRAM, re a l-tim e clock, crystal, power-fail control circuit, and battery The bq4850Y RTC Module is a non­ volatile 4,194,304-bit SRAM organ­

82C8167

Abstract: UM82C8167 UM82C8
Contextual Info: UMC UM82C8167 S S 2 S S S 2 S 2 Î Real-Time Clock RTC eatures Microprocessor compatible (8-bit data bus) Milliseconds through month counters 56 bits of RAM with comparator to compare the real time counter to the RAM data 2 IN TERRU PT OUTPUTS with 8 possible interrupt

Contextual Info: TLC04/MF4A-50, TLC14/MF4A100 BUTTERWORTH FOURTH-ORDER LOW PASS SWITCHED-CAPACITOR FILTERS D 2 97 0 , NOVEMBER 1 9 8 6 -R E V IS E D NOVEMBER 1988 D OR P PACKAGE Low Clock-to-Cutoff-Frequency Ratio Error T L C 0 4 /M F 4 A -5 0 . . . ± 0 .8 % T L C 1 4 /M F 4 A -1 0 0 . . . ± 1 %

UM61256FK-15

Abstract: um61256fs 15 UM61256FS-15 um61256f um61256fk15 UM61256FK UM61256FM-25 um61256 UM61256FK-12 um61256fs
Contextual Info: UM61256F Seríes 32K X a High Speed CMOS SRAM Features • * ■ ■ ■ Single +5V power supply ■ Access times: 12 /15/2 5 ns max. ■ Current: Operating: 150mA (max.) Standby: 12mA (max.) ■ Full static operation, no clock o r refreshing required Directly TTL compatible: All inputs and outputs

SN54ALS192

Abstract: 74ALS192
Contextual Info: SN54ALS192, SN54ALS193, SN74ALS192. SN74ALS193 SYNCHRONOUS 4 BIT UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR D 2 6 6 1 , D EC EM BE R 1 9 8 2 - R E V IS E O M A Y • Look-A head C irc u itry Enhances Cascaded C ounters • Fully S ynchronou s in C o u n t M odes

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

Contextual Info: UT54ACS 169/UT54ACTS 169 Radiation-Hardened 4-Bit Up-Down Binary Counters FEATURES • • • • • • • • • • Fully synchronous operation for counting and programming Internal look-ahead for fast counting Carry output for n-bit cascading Fully independent clock circuit

ic 4017 pin configuration

Abstract: pin diagram of IC 4017 n ic 4017 PIN DIAGRAM IC 4017 B operation of 4017 ic ic 4017 tl 4017 4017 counter IC 4017 DC 4017 IC
Contextual Info: SN 54H C4017, SN74HC4017 DECADE COUNTERS/DIVIDERS D 2 6 8 4 . DECEMBER 1 9 8 2 -R E V IS E D JUNE 1 9 8 9 Carry-Out Output for Cascading S N 5 4 H C 4 0 1 7 . . . J P AC KA G E S N 74H C 4017 N P AC KAG E Divide-by-N Counting ITO P V IE W DC Clock Input Circuit Allows Slow Rise

CIRCUIT DIAGRAM OF Bf 199

Contextual Info: TC4042BP/BF/BFN C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4042B QUAD CLOCKED "D " LATCH_ TC4042B contains fo u r circuits o f "D " type latches having common CLOCK input and POLARITY input. W hen POLARITY input is placed at "H " level, D input appears

NS16C450N

Contextual Info: TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEM ENT 0 3 0 9 6 , M A R C H 1 9 8 8 - R E V IS E O A P R IL 1 9 8 9 N DUAL-IN-LINE PACKAGE • Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to 216 - 1 and Generates an Internal 16 X

25275

Contextual Info: TE X A S IN S T R { L I N / I N T F O T s D Ê| 0033=127 TELECOM CIRCUITS r 3 T-75-11-37 TCM2101/2 PCM REPEATER DECEMBER 1982 Features GND M • • • • • • • PCM Signal amplification Two ALBO taps High Q or Low Q clock extraction Decision time adjustment

1414f

Abstract: QFP144-P-2626B QFP44-P-1414F RTC Real Time Clocks TC8521AM TC8512BY MC68B45
Contextual Info: Microcomputer Peripheral Controller LSI RTC Real Time Clocks Group Name Parts Name Function Summary Package TC8521AP DIP18-P-300A TC8521AM SOP20-P-300 RTC-2A Real Time Clock for Micro Computer. Hour, minutes, second, month, day, day of the week and year count with leap year operation. 4-bit I/O CPU Direct.