CY37128V Search Results

CY37128V-83

Abstract: 35VCCI
Contextual Info: CY37128V PRELIMINARY UltraLogic 3.3V 128-Macrocell ISR™ CPLD — tPD = 10.0 ns Features — tS = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • •

Contextual Info: PRELIMINARY CY37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD Features — tpD = 10 ns — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — t Co = 6 .5 ns — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

CY37128

Abstract: CY37128V
Contextual Info: 7256V Back PRELIMINARY CY37128V UltraLogicTM 3.3V 128-Macrocell ISRTM CLPD Features — tPD = 10 ns — tS = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • • • •

CY37128

Abstract: CY37128V
Contextual Info: CY37128V PRELIMINARY i k v / kv, UltraLogicT M 3.3V 128-Macrocell ISR CLPD Features — tpD = ns — ts = 5.5 ns • 128 m a cro c ells in eig h t logic blocks — tc o = 6.5 ns • 3.3V In-S ystem R eprog ram m ab le™ IS R ™ • P ro d uct-term clocking

Contextual Info: CY37128V PRELIMINARY UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

CY37128

Abstract: CY37128V-83 clcc 68 CY37128V
Contextual Info: PRELIMINARY CY37128V UltraLogicTM 3.3V 128-Macrocell ISRTM CLPD — tPD = 10 ns Features — tS = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • • • • • •

cy37128

Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Contextual Info: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

Ultra37128

Abstract: 37128VP100
Contextual Info: fax id: 6147 PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 125 MHz • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — tPD = 10 ns

Contextual Info: PREUM INAm Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

clcc land pattern

Abstract: CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern
Contextual Info: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

Device-List

Abstract: cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2
Contextual Info: Device List Adapter List Converter List for ALL-11 JUL. 2000 Introduction T he Device List lets you know exactly which devices the Universal Programmer currently supports. The Device List also lets you know which devices are supported directly by the standard DIP socket and which

CY37512P208-100UMB

Abstract: CY37512P208-100UM CY37032VP44-100AI CY37256P160-83UM CY37064P44-154YMB CY37256P160-125UMB CERAMIC leaded CHIP CARRIER CLCC 68
Contextual Info: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Abstract: CY37064P44-154YMB CY37512P208-100UMB
Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

Contextual Info: Press Release CYPRESS OFFERS Ultra37000  CPLDs IN FINE-PITCH BGA PACKAGES New Packages Save Board Space, Increase Reliability, Ease Manufacturing SAN JOSE, Calif., April 5, 1999  Cypress Semiconductor Corporation today announced that its Ultra37000 family of Complex Programmable Logic Devices CPLDs is being offered in Fine-Pitch

l0249

Abstract: CY37032VP44-100AI
Contextual Info: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

5962-9951902QYA

Abstract: CY37128P100-125AXC U208 5962-9952301QZC CERAMIC LEADLESS CHIP CARRIER CY37032P44-125JXC CY37512P256-100BGI CY37192 CY37256 CY37384
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes

D168K

Abstract: PALC22V10B-20DMB CY7C186A-20DMB CY7C109L CY7C408A-15DMB CY7C342B-25RMB palc22v10b20dmb PALCE22V10-30DMB PALC22V10-30DMB CY6116A35LMBSMD
Contextual Info: SMD Cross Reference Listed below are the SMDs for which Cypress is an approved source of supply. Please contact your local Cypress representative or see the Cypress website www.cypress.com for the latest SMD update. All part numbers that have a date in the PPL (Preferred

CY37032VP44-100AI

Abstract: 5962-9952502QZC 400BA
Contextual Info: Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

22V10-Macrocell

Abstract: 99522 PLD20RA10 22V10D 5962-89598 cy7c291 CY7C425 PALC22V10B CY6116A CY7C128A
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number 16K 2K x 8—CS Power-Down 24S CY7C128A 16K 2K x 8—CS Power-Down 24 CY6116A 64K 8K x 8—CS Power-Down 28S CY7C185A 256K 32K x 8—CS Power-Down 28 CY7C198 256K

CY37032VP44-100AI

Abstract: CY37064P44-154YMB
Contextual Info: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37032VP44-100AI

Contextual Info: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

CY37128P84-125JI

Contextual Info: 256 PRELIMINARY CY37128 UltraLogic 128-Macrocell ISR™ CPLD Features • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37256P160-125AXI

Abstract: CY37032P44-125JXC 5962-9952502QZC CY37128P100-125AXC CY37032V 5962-9952301QZC 5962-9952302QZC CY37064P100-125AXI CY37512VP208-66NI tea1400
Contextual Info: Ultra37000 CPLD Family 5V and 3.3V ISR High Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs ❐ JTAG interface for reconfigurability ❐ Design changes do not cause pinout changes ❐ Design changes do not cause timing changes

CY37032

Abstract: CY37032V CY37064 CY37064V CY37128 CY37128V CY37192 CY37256 CY37384 CY37512
Contextual Info: 1Ultra37000 Features Family Ultra37000: December 13, 1996 Revision: March 15, 2001 Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability